AMS

TEEMA Group; City Of London; On-site; GBP 70,000 - 110,000; Full time

Job summary

TEEMA Group is partnering with a leading semiconductor firm to hire an AMS verification lead. You will own verification strategy for mixed-signal subsystems, define modeling fidelity, and drive co-simulation flows across Spice and digital simulators.

You will develop analog behavioral models, build self-checking testbenches, and establish functional coverage for analog corner behavior. Collaboration with analog and DSP teams and sign-off for tape-out are key milestones.

Qualifications

• BS/MS in Electrical Engineering or related field with 5+ years of analog/mixed-signal verification experience.
• Hands-on expertise with AMS modeling and verification: Verilog-AMS and real-number modeling (SystemVerilog real / wreal).
• Proficiency in SystemVerilog with assertion-based verification skills and testbench architecture.
• Ability to model analog blocks at appropriate abstraction levels and validate against transistor-level references.
• Strong debugging skills across analog/digital boundary with structured test planning and coverage.
• Comfort reading analog schematics and collaborating with analog and DSP designers.

Responsibilities

• Own the verification strategy and test plan for mixed-signal subsystems from block level to top-level integration.
• Define modeling approach and fidelity tiers and document accuracy vs runtime trade-offs.
• Develop and validate analog behavioral models against transistor-level references.
• Build self-checking testbenches and reusable verification components for AMS and mixed-signal interactions.
• Drive AMS co-simulation flows (Spice/FastSpice with digital simulators) and manage setup, performance, and runtime trade-offs.
• Define functional coverage and assertions targeting analog corner behavior (saturation, overflow, loop stability).
• Debug and root-cause failures across the analog/digital boundary and drive to closure.
• Partner with analog and DSP designers to translate analog intent into checkable models and tests.
• Own sign-off for tape-out with coverage closure and explicit verification statements.
• Build and maintain regression infrastructure and flow automation to improve AMS throughput.
• Contribute to silicon bring-up and lab correlation for model validation.

Skills

AMS modeling

Verilog-AMS

SystemVerilog real/wreal

AMS co-simulation

assertion-based verification

testbench design

debugging analog/digital

Education

BS/MS in Electrical Engineering

Tools

Spectre AMS

FastSpice

Verilog-AMS

Job description

Job Title: AMS

Job ID: 89376

Location: Greater London, United Kingdom

What you will be doing:

• Own the verification strategy and test plan for our mixed-signal subsystems, from block level through subsystem and top-level integration.

• Define the modeling approach and fidelity tiers – decide what gets a real-number model, what needs Verilog-AMS, and where transistor-level co-sim is required – and document the accuracy/runtime trade-offs.

• Develop and validate analog behavioral models against transistor-level references, owning the model-vs-schematic equivalence checks that keep the abstraction honest.

• Build self-checking testbenches and reusable verification components for analog/digital interactions: CDR lock, adaptation and calibration loop convergence, mode and power-state transitions, clock dividers, deserializers, and clock-domain crossings.

• Drive AMS co-simulation flows (Spice/FastSpice coupled with digital simulators) and own their setup, performance, and runtime trade-offs.

• Define functional coverage and assertions that target analog corner behavior – saturation, overflow, polarity, loop stability, settling – not just digital state.

• Debug and root-cause failures across the analog/digital boundary, including discrepancies between behavioral and transistor-level results, and drive them to closure.

• Partner with analog and DSP designers to review specs, pin down interface contracts, and translate analog intent into checkable models, assertions, and tests.

• Own block- and subsystem-level verification sign-off for tape-out, including coverage closure and a clear statement of what AMS did and did not verify (functional vs. performance).

• Build and maintain regression infrastructure and flow automation, and improve AMS simulation throughput.

• Contribute to silicon bring-up and lab correlation, feeding measured behavior back into model validation.

What you must have:

• BS/MS in Electrical Engineering or related field, with 5+ years of analog/mixed-signal verification experience on complex SoCs or mixed-signal IP.

• Hands-on expertise with AMS modeling and verification: Verilog-AMS and real-number modeling (SystemVerilog real / wreal), and analog-digital co-simulation flows (e.g., Spectre AMS, FastSpice coupled with a digital simulator).

• Proficiency in SystemVerilog, with solid assertion-based verification skills and the ability to architect self-checking testbenches and reusable verification components.

• Demonstrated ability to model analog blocks at the appropriate level of abstraction and to validate those models against transistor-level references.

• Strong debug skills across the analog/digital boundary, with a structured approach to test planning, functional coverage, and closure.

• Comfort reading analog schematics and specifications and collaborating directly with analog and DSP designers.