Senior ALU Design Engineer — Hybrid RTL/Chisel

SiFive; Cambridge; Hybrid; GBP 70,000 - 95,000; Full time

Job summary

SiFive, a leader in RISC-V, seeks a hardware engineer to specify, design and implement new arithmetic operators for RISC-V instructions, including floating-point, vector, crypto and integer operations. Hybrid work with one office day per week.

You will optimize timing, area and power, perform unit and formal testing, and collaborate with the physical implementation team to drive targets for frequency, area and power.

Qualifications

• Masters or higher degree in electronic engineering or computer science with a strong mathematical background or related field.
• 2+ years of RTL design or related design experience.
• Academic or professional experience with arithmetic RTL design or CPU RTL design in Chisel, Verilog, SystemVerilog or VHDL.
• Knowledge of at least one object-oriented or functional programming language and willingness to adopt Chisel hardware generator design.
• Attention to detail and a focus on high-quality code and documentation.
• Ability to work well with others and share the belief that engineering is teamwork.
• This is a hybrid working position with 1 office day per week expected; more office days are possible if the successful candidate so prefers

Responsibilities

• Specify, design and implement new arithmetic operators for arithmetic RISC-V instructions, including floating-point, vector, crypto and integer operations.
• Optimize timing, area and power usage, or reduce latencies of existing operators
• Unit and formal testing for optimizations, writing new tests for new designs
• Work with the physical implementation team to optimize physical design to frequency, area, and power targets.
• Create documentation to a high standard and collaborate across teams and disciplines.

Skills

Mathematics

RTL design

Teamwork

Education

Master's degree in electronic engineering or computer science

Tools

Chisel

Verilog

SystemVerilog

VHDL

Job description

SiFive, a leader in RISC-V, seeks a hardware engineer to specify, design and implement new arithmetic operators for RISC-V instructions, including floating-point, vector, crypto and integer operations. Hybrid work with one office day per week.

You will optimize timing, area and power, perform unit and formal testing, and collaborate with the physical implementation team to drive targets for frequency, area and power.