Verification Manager

Codasip; Fen Ditton; On-site; GBP 90,000 - 130,000; Full time

Job summary

Codasip, a leader in CHERI‑RISC‑V architectures, seeks a DV Manager to expand the Verification team across multiple Design Centers in the UK, including Bristol and Cambridge.

You will drive project ownership, mentor engineers, and shape verification strategy while collaborating with cross‑functional teams to deliver secure, high‑quality IP across the Codasip portfolio, contributing to company strategy and architectural decisions.

Qualifications

• Extensive semiconductor verification leadership experience.
• Experience with CPU/ASIC verification methodologies (simulators, coverage, gate-level).
• Knowledge of RISC-V Architecture.
• Proven ability to manage workload in dynamic environment.
• Excellent leadership and communication skills.

Responsibilities

• Lead the expansion of the Verification team across Design Centers, aligning with company strategy.
• Collaborate with other Verification Leads to share responsibilities and optimize resources.
• Verify RISC-V processors and extensions.
• Take ownership of IP Verification projects and deliverables.
• Contribute to determining the company’s verification strategy.
• Provide technical leadership and build a culture of excellence in verification practices.
• Partner with cross-functional teams to optimize collaboration and project execution.
• Stay abreast of industry trends and advancements to drive innovation.

Skills

Leadership

Verification leadership

RISC-V

CPU verification

Tools

N/A

Job description

Maximise your chances of a successful application to this job by ensuring your CV and skills are a good match.

• Please note this role is only open to candidates currently located in and with working rights to the UK


• Location: Preferably based at one of our UK design centres (Bristol or Cambridge).Welcome to Codasip At Codasip, we’re redefining the future of computing.

Following a bold strategic pivot toward cyber-resilient semiconductor architectures, we are building next-generation processors and systems where security is embedded at the very core by design, not as an afterthought.

As we expand our portfolio of secure, CHERI-enabled technologies and focus on delivering architecture-first security solutions, there has never been a more exciting time to join. We are embarking on clean-sheet designs and expanding the teams of engineers who can establish high-quality working practices as they explore new ground.

Be part of a global team shaping the next era of secure computing where innovation, ownership, and impact go hand in hand.

The impact you’ll make

As a DV Manager, you will confront the technical challenges inherent in expanding our Verification team and capacity over multiple Design Centers.

Your role will be pivotal in shaping our company's strategy, focusing on both project aspects and broader organizational goals.

We are looking for a proactive leader who can share the workload with other Verification Leads, motivating and guiding our engineers to achieve their full potential.

You will:

• Lead the expansion of our Verification team and capacity over multiple Design Centers, building on top of established foundations and aligning efforts with company strategy and objectives.


• Collaborate with other Verification Leads to share responsibilities, ensuring effective management of workload and resources.


• Verify RISC-V processors and extensions.


• Take ownership of IP Verification projects.


• Contribute to determining the company’s strategy regarding verification.


• Tackle the challenges unique to Codasip and its customizable IP portfolio.


• Provide technical leadership and guidance to the Verification team, building a culture of excellence in Verification methodologies and processes.


• Partner with cross-functional teams to optimize collaboration and streamline project execution.


• Stay abreast of industry trends and advancements, leveraging insights to drive innovation and maintain our competitive edge.

What You Bring to The Table

• Extensive experience in semiconductor Verification with a desire to transition to the manager stream.


• Significant commercial experience with a variety of functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, coverage collection, gate level simulation, etc.).


• Knowledge of verifying CPU architectures or other complex IPs (GPUs, NNAs).


• Proven ability to manage workload effectively and prioritize tasks in a dynamic environment.


• Excellent leadership and communication skills, with the ability to motivate and inspire teams.


• Understanding of RISC-V Architecture.


• Knowledge of computer systems and architecture.


• Experience with advanced verification techniques.

Get to Know UsCodasip announces strategic pivot and divestitureCHERI-RISC-V standardisation status.

• Tariq Kurd | CHERITech'25Why Codasip went all‑in on CHERI – CHERI AllianceDepartmentUK VerificationEmployment TypeFull-TimeMinimum ExperienceManager/Supervisor