Senior Verification Engineer – RISC-V & CHERI Security (UK)

Codasip; West of England; Hybrid; GBP 60,000 - 90,000; Full time

Job summary

Codasip is seeking a Verification Engineer in the UK to verify RISC-V processors and extensions, develop test benches, and collaborate across disciplines on a brand-new platform. The role focuses on delivering end-to-end verification for complex CPUs and CHERI-enabled technologies within UK design centres in Cambridge or Bristol.

Ideal candidates have hands-on experience with SystemVerilog, Python, C++, and Rust, plus Linux automation, and a solid understanding of CPU architectures.

Qualifications

• Commercial experience with functional processor verification methodologies.
• Knowledge of verifying CPU architectures or other IP.
• Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, etc.
• Past verification ownership of a design block.
• User knowledge of Linux to enable automation of common tasks.
• Knowledge of versioning tools (Git, SVN).
• Knowledge of RISC-V Architecture.
• Good knowledge of computer systems and architecture.
• Analytical thinking and team collaboration skills.
• Ability to work effectively across teams to debug issues and find root causes.

Responsibilities

• Verify RISC-V processors and extensions.
• Develop verification solutions (e.g., test benches and test bench components, stimulus generation, formal environments).
• Collaborate with other engineers in a team responsible for the delivery of all verification activities related to a component or subsystem from start to finish.
• Define verification strategies for blocks and sub-systems, identifying and utilising the right tools.
• Review technical specifications, providing feedback from a verification perspective.
• Run simulations, hunt bugs and complete root cause analysis of complex issues.
• Define, estimate, prioritise and track your own work.
• Track and report verification metrics.
• Craft automated verification flows.

Skills

SystemVerilog

Python

C++

Rust

Linux

Git

SVN

RISC-V

Team collaboration

Tools

Git

SVN

Job description

Codasip is seeking a Verification Engineer in the UK to verify RISC-V processors and extensions, develop test benches, and collaborate across disciplines on a brand-new platform. The role focuses on delivering end-to-end verification for complex CPUs and CHERI-enabled technologies within UK design centres in Cambridge or Bristol.

Ideal candidates have hands-on experience with SystemVerilog, Python, C++, and Rust, plus Linux automation, and a solid understanding of CPU architectures.