Power Management Design Engineer - Flexible PTO & Equity

SiFive; Cambridge; On-site; GBP 152,000 - 186,000; Full time

Benefits offered by this job

Flexible PTO

Health benefits

Vision and dental benefits

401(k) plan

Employee stock options

Job summary

SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to join our team. You will create power management, reset, and clocking solutions that power the central nervous system for cutting-edge RISC-V CPU and SoC IP designs.

You will work in a fast-paced environment to bring hardware IP to market with high quality and performance. As part of a cross-functional team, you will ensure robust DP and DVFS strategies, collaborate with architecture, DV, physical design,

Qualifications

• 3+ years in CPU/SoC clocking, reset, and power-management logic.
• Proficiency with HDL design: Verilog/SystemVerilog/VHDL.
• Knowledge of DFT, MBIST, Debug and error handling in CPU designs.
• RTL quality checks (Lint, CDC, RDC) with Spyglass experience.

Responsibilities

• Understand power management requirements with architecture team.
• Design core clocking, reset and PMU solutions.
• Document and share knowledge; collaborate on design.
• Perform initial sandbox verification and work with DV team on test plans.
• Collaborate with physical design to meet freq, area and power goals.
• Collaborate with software team to enable PM features.

Skills

Power management

Clocking

Reset design

DVFS

RTL design

Verilog

SystemVerilog

VHDL

Lint

CDC

RDC

AMBA AXI

GitHub

Jira

Confluence

Education

BS/MS in EE/CE/CS

Tools

Spyglass

AMBA protocols

Job description

SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to join our team. You will create power management, reset, and clocking solutions that power the central nervous system for cutting-edge RISC-V CPU and SoC IP designs.

You will work in a fast-paced environment to bring hardware IP to market with high quality and performance. As part of a cross-functional team, you will ensure robust DP and DVFS strategies, collaborate with architecture, DV, physical design,