Power Integrity & EMIR Engineer for SoC Signoff

Aion Silicon Ltd; Greater London; On-site; GBP 90,000 - 120,000; Full time

Job summary

Aion Silicon Ltd is seeking an experienced EMIR / Power Integrity Engineer to join the SoC Physical Design team in London. You will own PDN planning, EMIR verification, and signoff for advanced semiconductor designs, driving ECOs and signoff closure.

Responsibilities include PDN optimization, IR drop analyses, EMIR signoff, and automation of flows using scripting languages. Collaboration across Physical Design, RTL, Package, and Reliability is essential.

Qualifications

• Bachelor's or Master's in Electrical/Electronics Engineering or related field.
• 5+ years of ASIC/SoC EMIR experience.
• Knowledge of UPF and low-power design methodologies.
• Experience developing signoff methodologies and CAD automation flows.
• Understanding of package parasitics and power delivery architecture.
• Strong analytical, debugging, and communication skills.

Responsibilities

• Perform Power Integrity and EMIR analysis for complex SoC, subsystem, and IP designs.
• Develop, analyze, and optimize PDN to meet performance, power, and reliability requirements.
• Execute Static IR Drop, Dynamic IR Drop, and Electromigration (EM) analysis throughout the design cycle.
• Define simulation methodologies, run setups, and signoff criteria for power integrity verification.
• Develop and enhance CAD-based EMIR analysis flows with timing, package, and board abstractions.
• Identify, debug, and root-cause EM, Static IR, and Dynamic IR violations.
• Provide and implement ECO solutions to resolve power integrity violations (grid enhancements, strap optimization, decap insertion, routing).
• Validate ECO effectiveness through iterative EMIR analysis and signoff closure.
• Collaborate with Physical Design, CAD, RTL, Package, and Reliability teams to achieve goals.
• Automate analysis, debugging, and reporting flows using Tcl, Python, Perl, or Shell scripting.
• Support advanced technology nodes and contribute to methodology development.

Skills

ASIC/SoC EMIR experience

Power Integrity analysis

Scripting languages (Tcl, Python, Perl

Education

Bachelor's or Master's in Electrical/Electronics Engineering

Tools

Cadence Voltus

Ansys RedHawk/RedHawk-SC

Synopsys PrimeRail/PrimePower

Cadence Innovus

Synopsys ICC2 / FC_SHELL

Job description

Aion Silicon Ltd is seeking an experienced EMIR / Power Integrity Engineer to join the SoC Physical Design team in London. You will own PDN planning, EMIR verification, and signoff for advanced semiconductor designs, driving ECOs and signoff closure.

Responsibilities include PDN optimization, IR drop analyses, EMIR signoff, and automation of flows using scripting languages. Collaboration across Physical Design, RTL, Package, and Reliability is essential.