Senior Physical Design Engineer: ASIC/SoC PPA & Sign-off

Fractile; Greater London; On-site; GBP 70,000 - 90,000; Full time

Job summary

A pioneering AI technology firm in Greater London is seeking a highly skilled Senior/Principal Physical Design Engineer to lead the physical implementation of next‑generation chip designs. This role involves driving complex IC designs from synthesis to sign‑off, collaborating with cross‑functional teams to optimise performance, power, and area. Candidates should have a strong background in EDA tools and advanced technology nodes, alongside excellent problem-solving abilities and teamwork skills.

Qualifications

• 7+ years of experience in physical design for advanced technology nodes.
• Strong proficiency in EDA tools for place & route, STA, and sign‑off.
• Experience with low‑power design methodologies and power optimisation techniques.

Responsibilities

• Drive the physical implementation of ASIC/SoC designs.
• Work on synthesis, timing analysis, and optimisation to achieve best metrics.
• Collaborate with DFT engineers to integrate design‑for‑test structures.

Skills

Physical Design

Power Optimisation

Timing Analysis

Scripting Languages

Collaboration

Education

Bachelor’s, Master’s, or PhD in Electrical Engineering or related field

Tools

Cadence Innovus

Synopsys ICC2

Mentor Graphics Calibre

Job description

A pioneering AI technology firm in Greater London is seeking a highly skilled Senior/Principal Physical Design Engineer to lead the physical implementation of next‑generation chip designs. This role involves driving complex IC designs from synthesis to sign‑off, collaborating with cross‑functional teams to optimise performance, power, and area. Candidates should have a strong background in EDA tools and advanced technology nodes, alongside excellent problem-solving abilities and teamwork skills.