Physical Design, Static Timing Analysis, Layout based with 3 years experience

Sevya Multimedia; Girton; Presencial; GBP 7100 - 12.000; Jornada completa

Descripción de la vacante

Sevya Multimedia is hiring a full-time, on-site Physical Design Engineer to lead floorplanning, placement, CTS, routing and layout optimization for complex SoCs. You will run static timing analyses, assess signal integrity, power, and physical verification reports, and implement fixes to meet performance targets.

You will collaborate with architecture and RTL teams, maintain CAD flows, prepare constraint files, and support tape-out activities while documenting methodologies and participating in

Formación

• Hands-on experience in physical design, STA, and layout for semiconductor devices.
• Proficiency with CAD tools for physical design and timing analysis.
• Experience with floorplanning, CTS, routing, DRC/LVS, and timing closure.

Responsabilidades

• Perform physical design implementation tasks: floorplanning, placement, CTS, routing, layout optimization.
• Run and analyze static timing, signal integrity, power, and physical verification reports.
• Collaborate with architecture and RTL teams; prepare constraint files and CAD flows.
• Support tape-out activities and document methodologies.

Conocimientos

CAD tools

Static Timing Analysis

Layout optimization

Floorplanning

Python scripting

Team collaboration

Digital SoC architecture

Educación

Bachelor’s or Master’s degree in Electrical/Electronics/CE

Herramientas

Cadence

Synopsys

Descripción del empleo

Company Description

Sevya Multimedia provides reliable, high-quality engineering services to leading global semiconductor product companies, with a strong focus on IoT and intelligent systems. The company specializes in developing and verifying IP, SoC, and embedded systems that help accelerate customers’ product roadmaps. Sevya works in close collaboration with client ecosystems to deliver solutions that integrate seamlessly into complex semiconductor environments. Team members gain exposure to cutting-edge technologies, diverse projects, and global industry best practices.

Role Description

This is a full-time, on-site Physical Design Engineer role with a focus on Static Timing Analysis and Layout, based in Hyderabad/Bengaluru or other locations as rquired. The role involves performing physical design implementation tasks such as floorplanning, placement, clock tree synthesis, routing, and layout optimization for complex SoCs. The engineer will run and analyze static timing, signal integrity, power, and physical verification reports, and apply fixes to meet performance, power, and area targets. Day-to-day responsibilities include collaborating with architecture and RTL design teams, preparing constraint files, maintaining CAD flows, and ensuring design closure against project schedules. The position also requires documenting methodologies, participating in design reviews, and supporting tape-out activities.

Qualifications

• Design and visualization skills in Graphic Design and Graphics relevant to layout representation and documentation.
• Strong analytical and problem-solving abilities supported by Research experience for exploring design techniques and process improvements.
• Foundational understanding of Architecture concepts, especially digital and SoC architecture as related to physical implementation.
• Proficiency with Computer-Aided Design (CAD) tools for physical design, static timing analysis, and layout (e.g., Cadence, Synopsys, or similar EDA tools).
• Approximately 3 years of hands‑on experience in physical design, static timing analysis, and layout for semiconductor devices.
• Knowledge of industry‑standard flows for floorplanning, placement, CTS, routing, DRC/LVS, and timing closure.
• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related technical field.
• Ability to work collaboratively in cross-functional teams, communicate clearly, and manage tasks to meet project deadlines.
• Familiarity with low‑power design techniques, advanced process nodes, and scripting (e.g., Python, TCL) is an advantage.