ASIC Physical Design Engineer — Flexible Hours & Silicon

Nordic Semi; West of England; On-site; GBP 70,000 - 110,000; Full time

Benefits offered by this job

Competitive salary with incentives

Flexible working hours

Medical insurance

Family-friendly policies

Job summary

Nordic Physical Design Engineer role focuses on transforming advanced semiconductor designs into high-performance silicon. You will drive floorplanning, power delivery, place-and-route, CTS, timing closure, and tape-out while collaborating with design, verification and silicon teams.

You should have a BSc/MSc in Electronics Engineering and several years of chip implementation experience, plus Synopsys/Cadence tool proficiency, scripting in TCL/Python, and exposure to AI-assisted design tools.

Qualifications

• BSc/MSc in Electronics Engineering or similar.
• Several years of experience in chip implementation.
• Experience with Synopsys and Cadence IC tools for implementation and sign-off.
• Contributed to flow development and setup.
• Proficient in scripting languages such as TCL, Python or similar.
• Experience using AI-assisted tools to improve design productivity.

Responsibilities

• Floorplanning activities, macro placement and voltage area definition.
• Develop and implement robust power distribution networks.
• Execute Place & Route including CTS, congestion and timing closure.
• Perform physical verification and signoff ensuring foundry requirements are met.
• Analyze IR-drop, electromigration and reliability for power integrity.
• Drive ECOs and late-stage design optimizations for timing closure.
• Support silicon bring-up and tape-out with physical design input.
• Contribute to development of PD flows and automation scripts.

Skills

Chip implementation

Scripting TCL/Python

AI-assisted design

English communication

Flow development

Problem solving

Education

BSc/MSc Electronics Engineering

Tools

Synopsys IC tools

Cadence IC tools

Flow automation scripts

Job description

Nordic Physical Design Engineer role focuses on transforming advanced semiconductor designs into high-performance silicon. You will drive floorplanning, power delivery, place-and-route, CTS, timing closure, and tape-out while collaborating with design, verification and silicon teams.

You should have a BSc/MSc in Electronics Engineering and several years of chip implementation experience, plus Synopsys/Cadence tool proficiency, scripting in TCL/Python, and exposure to AI-assisted design tools.