Physical Design Engineer IC Resources Recruitment

Abundant Code; United Kingdom; Remote; GBP 70,000 - 110,000; Full time

Benefits offered by this job

Bonus scheme

RSUs

Flexible working options

Job summary

IC Resources Recruitment is seeking a Physical Design Engineer in Cambridgeshire, England. You will lead the physical implementation of CPU blocks through the full flow from synthesis to sign-off, working with RTL, architecture and STA teams.

The role requires hands-on PD experience, strong scripting (TCL/Python/Perl) and proficiency with industry tools such as Innovus, ICC2 and Fusion Compiler. Flexible work options are offered.

Qualifications

• Significant hands-on experience in Physical Design for complex ASIC or CPU/SoC designs.
• Proficient in the complete implementation flow: floorplanning, place-and-route, clock tree synthesis and physical sign-off.
• Proficient scripting skills in TCL, Python, or Perl.

Responsibilities

• Lead the physical implementation of advanced CPU blocks from synthesis to sign-off.
• Handle floorplanning, power planning, placement, clock tree synthesis, routing and physical verification.
• Collaborate with RTL, architecture, STA and methodology teams to optimize performance, power and area.

Skills

ASIC/CPU/SoC experience

Scripting (TCL/Python/Perl)

Education

Electrical/Electronic Engineering

Computer Engineering

Tools

Innovus

ICC2

Fusion Compiler

Job description

Physical Design Engineer Overview

• Company Name: IC Resources Recruitment
• Job Role: Physical Design Engineer
• Qualifications: Not Specified
• Category: IT Jobs
• Job Type: Full Time
• Location: Cambridge

A leading innovator in next-generation compute architectures is seeking an experienced Physical Design Engineer to join their team in Cambridgeshire, England. This role offers an attractive base salary, a bonus scheme, RSUs, and flexible work options.

Key Responsibilities

• Lead the physical implementation of advanced CPU blocks from synthesis to sign-off.
• Take charge of key physical design tasks such as floorplanning, power planning, placement, clock tree synthesis, routing, and physical verification.
• Collaborate closely with RTL, architecture, static timing analysis (STA), and methodology teams to optimize designs for performance, power, and area.
• Identify and resolve timing, congestion, power, and DRC/LVS issues throughout the implementation process.
• Develop and improve automation, flows, and methodologies using scripting languages like TCL, Python, or Perl.
• Support design closure across advanced process technologies and contribute to the establishment of best practices for future projects.
• Work with cross-functional teams to ensure the delivery of high-quality silicon within tight project timelines.

Ideal Background

• A degree in Electrical/Electronic Engineering, Computer Engineering, or a related field.
• Significant hands-on experience in Physical Design for complex ASIC or CPU/SoC designs.
• Experience with the complete implementation flow, including floorplanning, place and route, clock tree synthesis, and physical sign-off.
• Familiarity with industry-standard EDA tools such as Innovus, ICC2, Fusion Compiler, or similar.
• A solid understanding of timing closure, power optimization, and physical verification methodologies.
• Proficient scripting skills in TCL, Python, or Perl.

Benefits

• Attractive base salary with a bonus scheme.
• Restricted Stock Units (RSUs) as part of the compensation package.
• Flexible working options to accommodate various work-life balance needs.

For more information, please contact Jordan Browne at IC Resources.

Degree Requirement: Not Specified

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