Lead AI Accelerator PPA Engineer

Fractile; West of England; On-site; GBP 90,000 - 150,000; Full time

Benefits offered by this job

Private Medical

Contributory Pension

25 Days holiday

Equity & Ownership

Job summary

Fractile seeks a senior hardware engineer to accelerate the clock speed of frontier AI inference by optimizing datapath RTL and PPA closure. You will own end-to-end optimization, from architectural trade-offs to timing-aware RTL, collaborating with PD and silicon teams to deliver measurable PPA gains on production silicon.

The role requires extensive experience with fixed/float/quantized arithmetic, low-power techniques, and hands-on use of synthesis and STA tools to close timing on critical

Qualifications

• Strong datapath microarchitecture background with pipeline, retiming, and area trade-offs.
• Track record of driving datapath PPA closure end-to-end and validating impact against targets.
• Knowledge of fixed-point, floating-point, and/or quantized arithmetic design.
• Deep understanding of PPA trade-off analysis and translating targets into RTL/microarchitectural decisions.
• Experience with low-power design techniques.
• Experience writing timing-aware datapath RTL and iterating against synthesis/STA feedback to close timing on critical paths.
• Familiarity with synthesis tools (e.g. Synopsys DC/Fusion Compiler, Cadence Genus), and datapath IP/generator libraries (e.g. DesignWare).
• Demonstrated, measurable PPA improvements on production datapath or compute silicon.
• Experience with formal verification or equivalence checking.
• Physical design awareness to collaborate with PD engineers on PPA closure.

Skills

Datapath microarchitecture

PPA closure experience

RTL design for timing

Fixed/float/quantized arithmetic

PPA trade-off analysis

Low-power design techniques

Synthesis/STA feedback

Formal verification

Physical design collaboration

Tools

Synopsys Design Compiler/Fusion Compiler

Cadence Genus

DesignWare IP

Job description

Fractile seeks a senior hardware engineer to accelerate the clock speed of frontier AI inference by optimizing datapath RTL and PPA closure. You will own end-to-end optimization, from architectural trade-offs to timing-aware RTL, collaborating with PD and silicon teams to deliver measurable PPA gains on production silicon.

The role requires extensive experience with fixed/float/quantized arithmetic, low-power techniques, and hands-on use of synthesis and STA tools to close timing on critical