Lead PPA Engineer

Fractile; West of England; On-site; GBP 90,000 - 150,000; Full time

Benefits offered by this job

Private Medical

Contributory Pension

25 Days holiday

Equity & Ownership

Job summary

Fractile seeks a senior hardware engineer to accelerate the clock speed of frontier AI inference by optimizing datapath RTL and PPA closure. You will own end-to-end optimization, from architectural trade-offs to timing-aware RTL, collaborating with PD and silicon teams to deliver measurable PPA gains on production silicon.

The role requires extensive experience with fixed/float/quantized arithmetic, low-power techniques, and hands-on use of synthesis and STA tools to close timing on critical

Qualifications

• Strong datapath microarchitecture background with pipeline, retiming, and area trade-offs.
• Track record of driving datapath PPA closure end-to-end and validating impact against targets.
• Knowledge of fixed-point, floating-point, and/or quantized arithmetic design.
• Deep understanding of PPA trade-off analysis and translating targets into RTL/microarchitectural decisions.
• Experience with low-power design techniques.
• Experience writing timing-aware datapath RTL and iterating against synthesis/STA feedback to close timing on critical paths.
• Familiarity with synthesis tools (e.g. Synopsys DC/Fusion Compiler, Cadence Genus), and datapath IP/generator libraries (e.g. DesignWare).
• Demonstrated, measurable PPA improvements on production datapath or compute silicon.
• Experience with formal verification or equivalence checking.
• Physical design awareness to collaborate with PD engineers on PPA closure.

Skills

Datapath microarchitecture

PPA closure experience

RTL design for timing

Fixed/float/quantized arithmetic

PPA trade-off analysis

Low-power design techniques

Synthesis/STA feedback

Formal verification

Physical design collaboration

Tools

Synopsys Design Compiler/Fusion Compiler

Cadence Genus

DesignWare IP

Job description

About Fractile

Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.

The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems.

Requirements

• Strong datapath microarchitecture background: pipelining, retiming, and parallelism-vs-area trade-offs for PPA
• Track record of driving datapath PPA closure end-to-end: identifying bottlenecks, proposing RTL changes, and validating impact against targets
• Good knowledge of fixed-point, floating-point, and/or quantized arithmetic design
• Deep understanding of PPA trade-off analysis, and the ability to translate PPA targets into concrete RTL and microarchitectural decisions
• Experience with low-power design techniques
• Experience writing timing-aware datapath RTL and iterating against synthesis/STA feedback to close timing on critical paths
• Familiarity with synthesis tools (e.g. Synopsys Design Compiler/Fusion Compiler, Cadence Genus), and datapath IP/generator libraries (e.g. DesignWare)
• Demonstrated, measurable PPA improvements delivered on production datapath or compute silicon
• Experience with formal verification or equivalence checking
• Physical design awareness sufficient to collaborate effectively with PD engineers on PPA closure

Nice to Have

• Experience with AI/ML accelerator datapath (e.g. systolic arrays, MAC/tensor engines) or other high-performance compute chip architectures
• Experience with static timing analysis tools (e.g. PrimeTime, Tempus)

How we work

• Ownership and execution: you will have full agency to drive your work forward
• Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
• Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
• Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
• Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is

What we offer

• Competitive salary: A competitive salary reflective of your experience and the specialist nature of the role.
• Equity & Ownership: meaningful equity so everyone shares in the value creation.
• Benefits: Private Medical, Dental and Vision, Contributory Pension, 25 Days holiday plus bank holidays and Life/Critical Illness Insurance.
• Diverse & fun office: we believe the hardest problems get solved by the broadest range of minds. We are committed to Equal Employment Opportunity through attracting and retaining a diverse team and building an inclusive environment.

Fractile is seeking to increase the clock speed of global progress, one chip at a time. We’ve recently raised $220M from investors including Founders Fund and Accel and our most important work lies ahead. Join us!

Export controls

Our work involves technologies subject to UK, US and other international export control regulations. Certain roles may require additional eligibility checks to ensure compliance with applicable law. We'll be transparent about this throughout the hiring process.