Lead DFT Engineer: AI Accelerator Architect with Equity

Fractile; West of England; On-site; GBP 90,000 - 150,000; Full time

Benefits offered by this job

Private Medical

Dental and Vision

Contributory Pension

25 Days holiday plus bank holidays

Life/Critical Illness Insurance

Equity & Ownership

Job summary

Fractile is seeking a Lead/Principal DFT Engineer to own the DFT architecture for a major AI accelerator SoC, driving strategy, signoff, and tool integration. You will shape hierarchical DFT for multi-core designs and work with RTL/physical teams to ensure timing closure and robust production test.

Ideal candidates have 10+ years in DFT for ASIC/SoC, with hands-on expertise in scan, ATPG, MBIST, and experience with Synopsys Tessent.

Qualifications

• 10+ years of experience in DFT for complex ASIC/SoC designs.
• Ownership of DFT architecture on at least one large tapeout.
• Deep expertise in scan, compression, ATPG, and MBIST.
• Experience with Synopsys Tessent and similar tools.
• Strong understanding of clocking, resets, power domains and physical constraints.
• Experience with silicon bring-up, debug and yield ramp.

Responsibilities

• Own and define the DFT architecture for a large AI accelerator SoC (scan, compression, MBIST, LBIST, boundary scan).
• Set DFT strategy, methodology, flow and signoff criteria.
• Drive integration of DFT tools and flows into the overall EDA environment.
• Define hierarchical DFT approach for multi-core designs and large memory systems.
• Define scan architecture, compression strategy, and ATPG approach.
• Define memory test and repair strategy for large embedded RAM.
• Establish power-aware and at-speed test strategies.
• Work closely with RTL and physical design to ensure clean DFT integration and timing closure.
• Work with test and product engineering teams to bring up and debug ATPG patterns on ATE, supporting production test and yield ramp.
• Mentor and guide DFT engineers.

Skills

DFT Architecture

ASIC/SoC DFT

ATPG/MBIST

Clocking/Power domains

Troubleshooting

Tools

Synopsys Tessent

Job description

Fractile is seeking a Lead/Principal DFT Engineer to own the DFT architecture for a major AI accelerator SoC, driving strategy, signoff, and tool integration. You will shape hierarchical DFT for multi-core designs and work with RTL/physical teams to ensure timing closure and robust production test.

Ideal candidates have 10+ years in DFT for ASIC/SoC, with hands-on expertise in scan, ATPG, MBIST, and experience with Synopsys Tessent.