Senior Digital Verification Architect — Chiplet & VIP Expert

Cadence Design Systems, Inc.; City of Edinburgh; In loco; GBP 110.000 - 150.000; Tempo pieno

Descrizione del lavoro

Cadence Design Systems, Inc. in Edinburgh is seeking a Digital Electronics Principal Verification Engineer to join a seasoned chiplet team. You will develop verification environments, UVM-based scoreboards and coverage, and collaborate with architects and design engineers.

The role requires 10+ years in microelectronics/EDA, Verilog RTL, MDV and formal verification, plus strong English and communication skills. Location: Edinburgh, on-site with Cadence tools and ISO-9001 collaboration.

Competenze

• 10+ years’ experience in microelectronics/EDA industry.
• Experience of Verilog RTL Design essential.
• Experience of Metric Driven Verification (MDV) essential.
• Experience of Formal Verification Methodologies essential.
• Excellent oral and written English essential.
• Self-motivated with planning, interpersonal and communication skills.

Mansioni

• Development of Verification and Emulation Environments for complex Chiplet Designs.
• Development of UVM-SV Scoreboards for self-checking regressions.
• Development of Functional Coverage as part of Metric Driven Verification Environments.
• Development of SystemVerilog Assertions for use in Formal and Simulation Environments.
• Development of Emulation Environments based on Cadence Palladium Emulator Product.
• Integration of Cadence Verification IP (VIP) for Simulation Environments.
• Integration of Accelerated VIP (AVIP) for Emulation Environments.
• Definition and Management of Verification Plans (vPlans) using Cadence vManager tools.
• Creation and Management of Automated Regression Environments, e.g. Jenkins, GIT.
• Participation in Technical Review Meetings and Checklist Reviews as part of ISO-9001.
• Close Collaboration with Architects and Design Engineers to debug complex test scenarios

Conoscenze

Verilog RTL Design

Metric Driven Verification

Formal Verification

English communication

Formazione

Degree in Electrical/Electronic Engineering

Strumenti

Cadence Palladium Emulator

Jenkins

GIT

Cadence vManager

Descrizione del lavoro

Cadence Design Systems, Inc. in Edinburgh is seeking a Digital Electronics Principal Verification Engineer to join a seasoned chiplet team. You will develop verification environments, UVM-based scoreboards and coverage, and collaborate with architects and design engineers.

The role requires 10+ years in microelectronics/EDA, Verilog RTL, MDV and formal verification, plus strong English and communication skills. Location: Edinburgh, on-site with Cadence tools and ISO-9001 collaboration.