High-Speed SerDes Research & Modeling Architect

IC Resources; Cambridge; On-site; GBP 65,000 - 90,000; Full time

Job summary

IC Resources is seeking a SerDes Architecture and Modelling Engineer for the UK, with options to base in Cambridge or the Thames Valley. The role prioritises research and architectural exploration over simple implementation, developing models and algorithms to probe next-generation high-speed links.

You will work across signal integrity, system modelling and collaboration with architects and IC designers to translate concepts into practical transceiver architectures, supporting analog, digital

Qualifications

• Experience in system-level modelling of communication systems or SerDes
• Understanding of signal integrity, jitter, noise, equalisation and link-performance analysis
• Ability to translate system requirements into block-level specifications
• Ability to collaborate with analog, digital, verification and architecture teams to validate models against simulations or measurements

Responsibilities

• Research and develop new concepts for high-speed serial communication systems
• Build system-level models to investigate, compare and optimise new architectures
• Develop signal processing algorithms and evaluate their impact on link performance
• Use MATLAB, Python or C++ to model communication systems and test new ideas
• Work with architects and IC designers to translate research concepts into practical transceiver architectures
• Analyse system limitations including signal integrity, noise, power and clock recovery
• Define link budgets and block-level specifications based on system requirements
• Support analog, digital and verification teams throughout the development process

Skills

System-level modelling

Signal processing

High-speed communication

Research

Algorithm development

Collaboration

Modelling software

Tools

MATLAB

Python

C++

Job description

IC Resources is seeking a SerDes Architecture and Modelling Engineer for the UK, with options to base in Cambridge or the Thames Valley. The role prioritises research and architectural exploration over simple implementation, developing models and algorithms to probe next-generation high-speed links.

You will work across signal integrity, system modelling and collaboration with architects and IC designers to translate concepts into practical transceiver architectures, supporting analog, digital