DFT Engineer for Next-Gen ASICs

IC Resources; Cambridge; On-site; GBP 60,000 - 90,000; Full time

Job summary

IC Resources is seeking a dedicated DFT Engineer to join a growing ASIC team in Cambridge. You will define and implement DFT strategies across chips, subsystems and IP, balancing test coverage with implementation complexity to deliver robust silicon for high-volume production.

You will work with Design, Verification, Physical Implementation and Product Engineering teams, insert and integrate scan, MBIST, EDT, SSN and IJTAG-based test infrastructures, and mentor peers while ensuring seamless

Qualifications

• Experience in modern ASIC/SoC development flows.
• Strong experience with Siemens Tessent DFT tools.
• Understanding of clocking, reset architecture and IP integration.
• Experience with ATPG, MBIST, and scan architectures.
• DFT verification and debugging across design cycles.
• Proficient in Tcl scripting; Python is a plus.

Responsibilities

• Define DFT strategies at chip, subsystem and IP level.
• Implement structural and functional DFT methodologies across ASIC designs.
• Insert and integrate scan, MBIST, EDT, SSN and IJTAG-based test infrastructure.
• Verify DFT implementation and debug issues throughout the design cycle.
• Support timing, power analysis and formal equivalence checking during sign-off.
• Work closely with Physical Design and Verification teams for integration.
• Support ATPG generation, silicon bring-up and manufacturing test.
• Mentor and support other engineers.

Skills

ASIC/SoC flows

Siemens Tessent DFT tools

Clocking & reset architecture

IP integration

ATPG

MBIST

Scan architecture

DFT verification & debugging

Tcl scripting

Python

Troubleshooting

Tools

IJTAG

EDT

SSN

Job description

IC Resources is seeking a dedicated DFT Engineer to join a growing ASIC team in Cambridge. You will define and implement DFT strategies across chips, subsystems and IP, balancing test coverage with implementation complexity to deliver robust silicon for high-volume production.

You will work with Design, Verification, Physical Implementation and Product Engineering teams, insert and integrate scan, MBIST, EDT, SSN and IJTAG-based test infrastructures, and mentor peers while ensuring seamless