SoC Design Engineer — Global Impact & Innovation

Microchip Technology Inc.; Rousset-Serre-Ponçon; On-site; EUR 65,000 - 90,000; Full time

Job summary

Microchip Technology Inc. in France is seeking a SoC Design Engineer in the MPU group to join the global Silicon Development Team. You will work on design and integration of complex IPs and subsystems into SoC, spanning microarchitecture, verification, and post-silicon support.

The role requires strong RTL coding with Verilog/SystemVerilog, knowledge of ARM AMBA, and collaboration across architecture and IP teams. Travel up to 25% and a path toward leadership are available.

Qualifications

• Strong understanding of SoC architecture fundamentals and digital design.
• Experience RTL coding using Verilog/SystemVerilog.
• Familiarity with ARM AMBA bus protocols.
• Experience with end-to-end SOC RTL to GDS to silicon release flow.
• Proficiency in scripting (Perl, Python, TCL).
• Knowledge of revision control tools (SVN, GIT).
• Awareness of AI-assisted development tools and responsible use.
• Excellent written and verbal communication skills.

Responsibilities

• Design and integration of complex IPs and subsystems into SoC
• Understand IP specifications and integrate into SOCs
• Perform RTL coding
• Develop verification plan for subsystems/SoC
• Collaborate with cross functional teams on performance, power analysis, and post-silicon validation
• Hold reviews to meet quality goals
• Support timing constraints and synthesis
• Power estimation and analysis

Skills

SoC Architecture

RTL Coding

ARM AMBA

RTL to GDS Flow

Scripting

Version Control

AI-assisted tools

Communication

Education

BSEE minimum

MSEE preferred

Job description

Microchip Technology Inc. in France is seeking a SoC Design Engineer in the MPU group to join the global Silicon Development Team. You will work on design and integration of complex IPs and subsystems into SoC, spanning microarchitecture, verification, and post-silicon support.

The role requires strong RTL coding with Verilog/SystemVerilog, knowledge of ARM AMBA, and collaboration across architecture and IP teams. Travel up to 25% and a path toward leadership are available.