Senior Systems Design Engineer - RTL, NoC & FPGA Emulation

QUALCOMM, Inc.; Guyancourt; Presencial; EUR 90 000 - 120 000; Tempo integral

Resumo da oferta

Qualcomm France S.A.R.L. seeks an experienced engineer to build system level platforms for RTL simulation and FPGA emulation. You will integrate CPUs/NSP and IPs such as interconnects or memory controllers in SystemVerilog and develop RTL testbenches for traffic generators and DDR memory models.

You will debug complex test scenarios, map platforms on emulators, and work in a Linux environment using ModelSim, Python, C, and C++ to deliver robust verification workflows.

Qualificações

• Bachelor's degree in Science/Engineering or related field with 2+ years ASIC design/verification experience.
• Master's degree with 1+ year ASIC design/verification experience or PhD with related work.
• Proficiency in SystemVerilog/Verilog and RTL verification.
• Experience with simulation tools and emulation platforms is preferred.

Responsabilidades

• Build and maintain system level platforms for RTL simulation and FPGA Emulation.
• Integrate CPUs/NSP and IPs such as interconnects or memory controllers into systemVerilog.
• Design RTL testbench modules like traffic generators or DDR memory models in SystemVerilog or C (DPI-C).
• Provide functional platforms by running and debugging integration and system level testcases.
• Map the full platform onto various Emulators.

Conhecimentos

SystemVerilog/Verilog

RTL Simulation

Debugging

Bus Protocols

DDR

SOC

Emulation

Python

C

C++

Formação académica

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Ferramentas

ModelSim

FPGA Emulation

Descrição da oferta de emprego

Qualcomm France S.A.R.L. seeks an experienced engineer to build system level platforms for RTL simulation and FPGA emulation. You will integrate CPUs/NSP and IPs such as interconnects or memory controllers in SystemVerilog and develop RTL testbenches for traffic generators and DDR memory models.

You will debug complex test scenarios, map platforms on emulators, and work in a Linux environment using ModelSim, Python, C, and C++ to deliver robust verification workflows.