Senior Systems Verification Engineer - Qualcomm - Sophia or Guyancourt, France

Qualcomm; Provence-Alpes-Côte d'Azur; Vor Ort; EUR 60.000 - 90.000; Vollzeit

Zusammenfassung

Qualcomm France S.A.R.L. seeks anEmbedded Systems Engineer to verify NoC interconnect behavior on custom emulators, ensuring CPU/NSP to DDR performance targets.

You will run bare metal tests and Linux benchmarks on latest CPU architectures and contribute to automation and tooling. The role requires strong C/assembly, ARM architectures, interconnects, and DSP/NSP knowledge; exposure to FPGA emulation, Linux kernel boot flow, and Python scripting is preferred.

Qualifikationen

• Essential: Verification Methodology, C / Assembly, Interconnect & Protocols minimum understanding.
• Desirable: Python, DRAM & Scheduling, Linux Kernel, Emulation or Silicon Validation experience.

Aufgaben

• Define and implement System & Performance validation plans for Qualcomm interconnects.
• Run bare metal testcases and Linux benchmarks on custom Emulators and NSP micro-benchmarks.
• Participate in infrastructure performance analysis, exploration and automation infrastructure.

Kenntnisse

C

ARM Assembly

ARM CPU Architecture

Interconnects & Protocols

DDR

DSP/NSP

Cache Coherency

Emulation methodology

FPGA

Debug tools

RTL Simulation

Ausbildung

Micro-electronics Engineer Diploma

Bachelor's degree in Science/Engineering

Tools

Python

Verilog

Linux Kernel boot flow

Jobbeschreibung

Company

Qualcomm France S.A.R.L.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

Qualcomm Interconnect Technology (QITC) has been breaking ground in interconnect design for 15 years and continues to innovate and deliver technology in line with the latest evolutions in SoC design. As part of Qualcomm Infrastructure division, QITC’s mission is to develop and deploy custom-built interconnect hardware IPs, software tools, exploration and verification methodologies, including Emulation platforms, so that SoC integration teams can quickly assemble SoCs with the desired Power, Performance, Area characteristics. The Job consists of verifying the NoC solutions behave as intended in the full System, and that the CPU / NSP to DDR performance targets are achieved.

Responsibilities

The engineer will be in charge of defining and implementing System & Performance validation plans centered around QCOM interconnects, by running bare metal testcases and Linux benchmarks for latest CPU architectures on custom Emulators, as well as NSP micro-benchmark execution. He or she will then participate in the infrastructure performance analysis, exploration and automatization infrastructure.

Skills And Experience

Good Low-level Software knowledge: C, ARM Assembly

Strong Systems understanding: ARM CPU Architecture, Interconnects & Protocols, DDR is a plus

DSP / NSP knowledge is a plus

Understand Cache and Coherency concepts

Understanding of Emulation methodology: FPGA, Debug tools, RTL Simulation

Additional Skills

Python, Verilog

Linux Kernel boot flow

Strong motivation and team spirit

Working environment: Linux

Educational Requirements

Micro-electronics or similar Engineer Diploma 5 years + 5 years of industry experience minimum

Technical Experience

Essential : Verification Methodology, C / Assembly, Interconnect & Protocols minimum understanding

Desirable: Python, DRAM & Scheduling, Linux Kernel, Emulation or Silicon Validation experience

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field.
• References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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