Senior Systems Design Engineer - Qualcomm - Sophia or Guyancourt - France

Qualcomm; Provence-Alpes-Côte d'Azur; Sur place; EUR 75 000 - 110 000; Plein temps

Résumé du poste

Qualcomm France S.A.R.L. seeks an experienced engineer to develop system level platforms for RTL simulation and FPGA emulation.

You will integrate CPUs/NSP and memory controllers in SystemVerilog, and design testbench modules (traffic generators, DDR models) using SystemVerilog or DPI-C in C. Responsibilities include building functional platforms, debugging integrations, and mapping the platform across multiple emulators, with strong focus on verification methodologies and early performance

Qualifications

• Good RTL development skills: SystemVerilog/Verilog integration and design.
• Systems understanding: Bus Protocols, DDR, SOC.
• Emulation methodologies knowledge.

Responsabilités

• Build and maintain system level platforms for RTL simulation and FPGA Emulation.
• Integrate CPUs/NSP and infrastructure IPs in SystemVerilog (and DPI-C).
• Design RTL testbench modules such as traffic generators or DDR memory models in SystemVerilog/C.
• Provide functional platforms by running and debugging integration and system level testcases.
• Map the full platform on various Emulators.

Connaissances

SystemVerilog

C

C++

Python

Formation

Micro-electronics or similar Engineer Diploma

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Outils

ModelSim

Linux

Description du poste

Company

Qualcomm France S.A.R.L.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

Qualcomm France-QITC develop interconnect for complex SoCs providing low power, higher system bandwidth, greater IP flexibility, fewer global wires and easier timing convergence as well as faster time to market than existing bus interconnects. QITC NoC solution includes a full suite of automated NoC Design Tools that improve designer productivity.

The Job is to create system level platforms and infrastructures necessary to conduct CPU / NSP to DDR functional verification and performance analysis on RTL simulation and FPGA Emulation for ground-breaking Qualcomm chips.

Responsibilities

The engineer will be in charge of building and maintaining system level platforms for RTL simulation and FPGA Emulation. It includes the integration in systemVerilog of CPUs and/or NSP and infrastructure IPs such as interconnects or memory controllers. He will be responsible for designing RTL modules for the testbench such as traffic generators or DDR memory models coding in systemVerilog or C language (DPI-C). He will have to provide functional platforms by running and debugging integration and system level testcases. The engineer will also participate in mapping the full platform on various Emulators.

Skills And Experience

Good RTL development skills: SystemVerilog/Verilog integration and design. RTL Simulation. Debugging

Systems understanding: Bus Protocols, DDR, SOC.

Emulation methodologies knowledge

Additional Skills

Python, C, C++

Strong motivation and team spirit

Working environment: Linux, ModelSim

Educational Requirements

Micro-electronics or similar Engineer Diploma

Technical Experience

Minimum 5-10 years experience

Essential

Verilog/SystemVerilog, Verification Methodology

Desired

Python, Emulation

Language requirements

French and English

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

• References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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