Senior/Staff ASIC Power & NoC Solutions Engineer

Qualcomm; Guyancourt; Sur place; EUR 90 000 - 130 000; Plein temps

Résumé du poste

Qualcomm France S.A.R.L. in Île-de-France invites experienced engineers to join the QITC Solutions Deployment Team. You will deploy and support NoC power technologies across Qualcomm SoCs, collaborating with Architecture, HW, SW, verification and post-silicon teams worldwide.

The role focuses on power architectures, interconnects, and ensuring SoC performance while maintaining cost efficiency. A master’s or PhD in a related field with several years of ASIC design experience is expected.

Qualifications

• Bachelor's degree in Science/Engineering with 4+ years ASIC experience.
• Master's degree in Science/Engineering with 3+ years ASIC experience.
• PhD in Science/Engineering with 2+ years ASIC experience.

Responsabilités

• Collaborate regularly with highly skilled experts across different teams (Architecture, Hardware, software, verification, emulation, ...) to ensure our technology is used efficiently in Qualcomm SoCs.
• Contribute to the definition of interconnect requirements and configuration in the various SoCs
• Provide support on power issues and technology of new QITC solutions and general technical support
• Help resolve NoC power micro-architecture and NoC power unit integration issues
• Participate in defining new or improved power architectures and power NoC units and be responsible for their validation in our technology
• Develop in-depth technical material and organize training for different teams worldwide

Connaissances

SoC architecture

Interconnect protocols

Power management

Debug & silicon bring-up

Communication skills

Formation

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Description du poste

Qualcomm France S.A.R.L. in Île-de-France invites experienced engineers to join the QITC Solutions Deployment Team. You will deploy and support NoC power technologies across Qualcomm SoCs, collaborating with Architecture, HW, SW, verification and post-silicon teams worldwide.

The role focuses on power architectures, interconnects, and ensuring SoC performance while maintaining cost efficiency. A master’s or PhD in a related field with several years of ASIC design experience is expected.