Senior HW IP Design Engineer - ASIC/SoC RTL

QUALCOMM, Inc.; Digne-les-Bains; On-site; EUR 65,000 - 90,000; Full time

Job summary

Qualcomm France S.A.R.L. is seeking an experienced HW IP designer to own unit specifications, develop RTL, and collaborate with architecture and verification teams across sites. You will drive microarchitecture definitions and ensure tight integration with SOC/ASIC flows.

Ideal candidates bring 4–5 years in microelectronics, strong RTL skills (Python/Verilog/C++), and experience with AMBA protocols. Proficiency in French and English is a plus in a multinational environment.

Qualifications

• Master’s or PhD level preferred with 2+ years ASIC design experience.
• Experience defining microarchitectures and writing clear specification documents.
• Proficiency in RTL coding/simulation and familiarity with SOC/ASIC design flows.
• Working knowledge of AMBA protocols (AXI, CHI) and English/French communication.

Responsibilities

• Derive unit specifications from Product Definition Requirements in collaboration with Architecture.
• Create RTL code and coordinate with verification team to ensure correct interpretation of specs.
• Work with verification and other teams to debug and implement ECOs.
• Engage with exploration and support teams across sites.

Skills

Python

Verilog

C++

French

English

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

Git

Svn

NcSim

Job description

Qualcomm France S.A.R.L. is seeking an experienced HW IP designer to own unit specifications, develop RTL, and collaborate with architecture and verification teams across sites. You will drive microarchitecture definitions and ensure tight integration with SOC/ASIC flows.

Ideal candidates bring 4–5 years in microelectronics, strong RTL skills (Python/Verilog/C++), and experience with AMBA protocols. Proficiency in French and English is a plus in a multinational environment.