HW IP Designer: SoC Interconnect & RTL Architect (AXI)

QUALCOMM, Inc.; Valbonne; On-site; EUR 70,000 - 110,000; Full time

Job summary

Qualcomm France S.A.R.L. invites an experienced HW IP designer to join Qualcomm France‑QITC and contribute to next generation semiconductor designs.

You will own units from specification to RTL and verification, collaborating with Architecture and Verification teams across sites. The role requires strong RTL, Python/Verilog/C++, and AMBA protocol knowledge in an international context.

Qualifications

• Master’s degree in electrical engineering or digital design.
• 4–5 years of microelectronics definition and design.
• Proficient in RTL coding/simulation and AMBA protocols.

Responsibilities

• Define unit specification from Product Definition Requirements with Architecture.
• Create verification-ready RTL and collaborate with verification team.
• Ensure specifications are understood and verified in all phases.
• Collaborate with exploration and support teams for results.
• Provide expertise for debug and ECO when needed.

Skills

Python

Verilog

C++

French/English

Education

Master’s degree in electrical engineering

Bachelor’s degree in science/engineering

PhD in science/engineering

Tools

Git/Svn

NcSim

Job description

Qualcomm France S.A.R.L. invites an experienced HW IP designer to join Qualcomm France‑QITC and contribute to next generation semiconductor designs.

You will own units from specification to RTL and verification, collaborating with Architecture and Verification teams across sites. The role requires strong RTL, Python/Verilog/C++, and AMBA protocol knowledge in an international context.