Senior Hardware Architect & 3D Chiplet Lead

Quantum Software; Grenoble; Sur place; EUR 120 000 - 180 000; Plein temps

Résumé du poste

Vertical Compute in Grenoble, France, is seeking a Hardware Architect and Team Lead to define and deliver next-generation 3D-integrated chiplet products for AI compute. You will own architecture, RTL, verification, DFT, and physical implementation while building and guiding the hardware team to tape-out-ready silicon.

You will collaborate with the memory design group and external partners to maximize bandwidth, performance, and energy efficiency, shaping the hardware foundation for scalable AI

Qualifications

• 15+ years of experience in ASIC/SoC hardware design and architecture.
• At least 3+ years leading engineering teams or managing design projects.
• Hands-on experience across the full ASIC development cycle: architectural specification, RTL design (SystemVerilog/Verilog), functional verification, DFT, physical implementation, and post-silicon bring-up.
• Proven track record of silicon tape-outs, preferably involving complex multi-die, chiplet, or 2.5D/3D heterogeneous packaging architectures.
• Deep technical understanding of hardware-software co-design, memory architectures, and hardware acceleration for AI compute workloads.
• Demonstrated experience managing internal engineering talent as well as external design service providers.
• Degree (B.S., M.S., or Ph.D.) in Electrical Engineering, Computer Engineering, Microelectronics, or a related discipline.
• Strong leadership, project management, and cross-functional communication skills with a focus on collaborative problem-solving.
• Fluency in English with strong written and verbal communication abilities.

Responsabilités

• Define, architect, and specify 3D-integrated chiplet products for AI compute workloads.
• Lead and manage the full process from initial architecture definition through FE RTL development, verification, DFT, physical implementation oversight, and post-silicon bring-up.
• Manage and mentor the internal hardware design team while directing external design service companies and IP vendors.
• Partner closely with the memory engineering team to co-optimize hardware architectures for AI processing, maximizing bandwidth, throughput, and power efficiency.
• Establish robust design methodologies, best engineering practices, and thorough review processes across the hardware flow to guarantee tape-out readiness and silicon success.

Connaissances

ASIC/SoC design

Team leadership

Hardware architecture

HW-SW co-design

Project management

Communication

Formation

B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, Microelectronics

Outils

SystemVerilog/Verilog

Description du poste

Vertical Compute in Grenoble, France, is seeking a Hardware Architect and Team Lead to define and deliver next-generation 3D-integrated chiplet products for AI compute. You will own architecture, RTL, verification, DFT, and physical implementation while building and guiding the hardware team to tape-out-ready silicon.

You will collaborate with the memory design group and external partners to maximize bandwidth, performance, and energy efficiency, shaping the hardware foundation for scalable AI