Hardware Architect and Team Lead

Quantum Software; Grenoble; Sur place; EUR 120 000 - 180 000; Plein temps

Résumé du poste

Vertical Compute in Grenoble, France, is seeking a Hardware Architect and Team Lead to define and deliver next-generation 3D-integrated chiplet products for AI compute. You will own architecture, RTL, verification, DFT, and physical implementation while building and guiding the hardware team to tape-out-ready silicon.

You will collaborate with the memory design group and external partners to maximize bandwidth, performance, and energy efficiency, shaping the hardware foundation for scalable AI

Qualifications

• 15+ years of experience in ASIC/SoC hardware design and architecture.
• At least 3+ years leading engineering teams or managing design projects.
• Hands-on experience across the full ASIC development cycle: architectural specification, RTL design (SystemVerilog/Verilog), functional verification, DFT, physical implementation, and post-silicon bring-up.
• Proven track record of silicon tape-outs, preferably involving complex multi-die, chiplet, or 2.5D/3D heterogeneous packaging architectures.
• Deep technical understanding of hardware-software co-design, memory architectures, and hardware acceleration for AI compute workloads.
• Demonstrated experience managing internal engineering talent as well as external design service providers.
• Degree (B.S., M.S., or Ph.D.) in Electrical Engineering, Computer Engineering, Microelectronics, or a related discipline.
• Strong leadership, project management, and cross-functional communication skills with a focus on collaborative problem-solving.
• Fluency in English with strong written and verbal communication abilities.

Responsabilités

• Define, architect, and specify 3D-integrated chiplet products for AI compute workloads.
• Lead and manage the full process from initial architecture definition through FE RTL development, verification, DFT, physical implementation oversight, and post-silicon bring-up.
• Manage and mentor the internal hardware design team while directing external design service companies and IP vendors.
• Partner closely with the memory engineering team to co-optimize hardware architectures for AI processing, maximizing bandwidth, throughput, and power efficiency.
• Establish robust design methodologies, best engineering practices, and thorough review processes across the hardware flow to guarantee tape-out readiness and silicon success.

Connaissances

ASIC/SoC design

Team leadership

Hardware architecture

HW-SW co-design

Project management

Communication

Formation

B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, Microelectronics

Outils

SystemVerilog/Verilog

Description du poste

About Us

AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.

Why Now

After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.

About the role:

We are looking for a Hardware Architect and Team Lead with strong hardware architecture expertise to lead the definition, architecture, and execution of our next-generation 3D-integrated chiplet products.

In this role, you will be responsible for architecting and specifying chiplet products developed by Vertical Compute integrated in 3D, ensuring they leverage our proprietary Vertical Integrated Memory (VIM™) technology to address complex AI computation challenges, collaborating closely with the memory design team and the SW Team in charge of the AI application and AI compiler development.

You will own the complete end-to-end hardware engineering lifecycle from architecture definition and specification up to final silicon tape-out and bring-up (architecture, front-end RTL development, verification, DFT, physical implementation, and silicon bring-up), building and leading the internal hardware team. You will coordinate with external design service companies, Research partners and Program Management Office to ensure the smooth running of the project.

Key Responsibilities

• Architecture & Chiplet Specification: Define, architect, and specify 3D-integrated chiplet products for AI compute workloads, taking full advantage of Vertical Compute’s VIM™ memory technology.
• End-to-End Process Ownership: Lead and manage the full process from initial architecture definition through FE RTL development, functional verification, Design-For-Test (DFT), physical implementation oversight, and post-silicon bring-up.
• Team Leadership: Manage and mentor the internal hardware design team while directing external design service companies and IP vendors to ensure high-quality, on-schedule delivery.
• Cross-Functional Collaboration with Memory Team: Partner closely with the memory engineering team to co-optimize hardware architectures for AI processing, maximizing bandwidth, throughput, and power efficiency.
• Execution & Quality Assurance: Establish robust design methodologies, best engineering practices, and thorough review processes across the hardware flow to guarantee tape-out readiness and silicon success.

About the team

This role leads the Hardware Design team within Vertical Compute's Product & System organization, partnering closely with our cross-functional engineering teams in Memory Design, Packaging, and System Architecture. We foster a highly collaborative, transparent, and inclusive environment where strong technical alignment and continuous innovation are central to solving the industry's memory bottleneck.

About who you are

• 15+ years of experience in ASIC/SoC hardware design and architecture, with at least 3+ years leading engineering teams or managing design projects.
• In-depth hands‑on expertise across the full ASIC development cycle: architectural specification, RTL design (SystemVerilog/Verilog), functional verification, DFT strategies, physical implementation, and post-silicon bring-up.
• Proven track record of successful silicon tape‑outs, preferably involving complex multi‑die, chiplet, or 2.5D/3D heterogeneous packaging architectures.
• Deep technical understanding of hardware‑software co‑design, memory architectures, and hardware acceleration for AI compute workloads.
• Demonstrated experience managing internal engineering talent as well as managing external design service providers.
• Degree (B.S., M.S., or Ph.D.) in Electrical Engineering, Computer Engineering, Microelectronics, or a related discipline.
• Strong leadership, project management, and cross‑functional communication skills with a focus on collaborative problem‑solving.
• Fluency in English with strong written and verbal communication abilities.

Location

Grenoble (France)

QUANTUM ROLE CONTEXT | Appended by Quantum.Jobs v2

Role context:

This role exists to bridge high-level system requirements with physical silicon implementation in advanced semiconductor development. Situated between executive engineering management and specialized design units, the hardware architecture lead defines product specifications and oversees chip development lifecycles. By coordinating internal engineering teams and external foundry services, professionals in this functional position ensure complex microarchitectural designs transition effectively from initial logic specifications to verified physical silicon, supporting organizational efforts to solve critical compute and memory bottlenecks.

Quantum ecosystem relevance:

While primarily focused on classical high-performance semiconductor architectures, this role type indirectly supports the broader quantum ecosystem through enabling infrastructure. Advanced packaging, high-density memory integration, and 3D chiplet architectures serve as critical foundational technologies for hybrid classical-quantum computing stacks. Hardware engineering leadership in semiconductor integration provides the scalable classical processing, low-latency interconnects, and high-bandwidth memory controllers necessary to interface with, control, and process readout data from emerging quantum processing units.

Capability signals

• Strategic technical leadership across full application-specific integrated circuit hardware development lifecycles
• Expertise in 3D-integrated chiplet architectures and advanced microelectronic packaging integration strategies
• Cross-functional coordination of internal design personnel, software teams, and external foundry partners
• Advanced proficiency in microarchitecture definition, register-transfer level design, and functional hardware verification
• Mastery of hardware-software co-design principles to optimize throughput, bandwidth, and energy efficiency