Senior FPGA Engineer — RF DSP & SoC Integration

Alta Ares; Paris; Sur place; EUR 60 000 - 100 000; Plein temps

Résumé du poste

Alta Ares seeks an experienced FPGA engineer to own RTL development for RF processing and EW capabilities. You will define requirements with systems and algorithm teams, build RTL modules in VHDL or SystemVerilog, and balance DSP algorithms against hardware resources.

You will integrate digital down-conversion, filtering, channelization, and FFT, while establishing verification methods and bringing designs up on target boards. Collaboration across RF, software, and systems is essential.

Qualifications

• MSc in Electrical Engineering, Electronics, Signal Processing, or related field.
• Strong RTL development experience in VHDL or SystemVerilog for DSP.
• Experience with SoC FPGAs: synthesis, timing, hardware debugging.
• Knowledge of sampled signals, frequency conversion, digital filtering, spectral analysis.
• Ability to reason across FPGA, processor and RF hardware boundaries.
• Familiarity with MATLAB, Simulink, Python; HLS is a plus.
• Familiar with RF measurements and lab equipment is a plus.

Responsabilités

• Own FPGA function development from architecture to hardware validation.
• Define processing requirements with systems and algorithms teams.
• Build RTL modules in VHDL/SystemVerilog for RF processing.
• Adapt DSP algorithms for FPGA implementation with resource balancing.
• Integrate acquisition and processing chains: down-conversion, filtering, FFT.
• Establish verification methods and testbenches for validation.
• Connect logic to RF converters and embedded processors.
• Bring up FPGA designs on target boards and troubleshoot.
• Contribute to lab and field testing with cross-disciplinary teams.
• Maintain design records, interface specs, and validation evidence.

Connaissances

RTL development

VHDL/SystemVerilog

SoC FPGA

DSP & signal processing

Synthesis & timing analysis

Hardware debugging

MATLAB/Simulink

Python

Formation

MSc in Electrical Engineering or related field

Outils

MATLAB

Simulink

Python

HLS

Description du poste

Alta Ares seeks an experienced FPGA engineer to own RTL development for RF processing and EW capabilities. You will define requirements with systems and algorithm teams, build RTL modules in VHDL or SystemVerilog, and balance DSP algorithms against hardware resources.

You will integrate digital down-conversion, filtering, channelization, and FFT, while establishing verification methods and bringing designs up on target boards. Collaboration across RF, software, and systems is essential.