FPGA Radar Engineer — Advanced Radar Processing for Defense

Alta Ares; Paris; Sur place; EUR 90 000 - 130 000; Plein temps

Résumé du poste

Alta Ares seeks an experienced FPGA engineer to translate radar sensing requirements into RTL in VHDL/Verilog, enabling reliable drone detection for FMCW and pulsed radar systems.

You will collaborate across RF, electronics, and software teams, defining data flow, processing budgets, and implementation approaches while validating designs with testbenches and hardware-in-the-loop testing.

Qualifications

• Master's degree or equivalent in Electrical Engineering, Signal Processing, Applied Physics, or a related field.
• Strong DSP foundations including FFT, filtering, windowing and fixed-point precision.
• Experience turning radar processing concepts into RTL code.
• Experience developing testbenches and validating processing chains with hardware-in-the-loop.

Responsabilités

• Turn radar sensing requirements into FPGA designs that support reliable drone detection.
• Define how radar data is acquired, processed, and delivered across RF, electronics and software teams.
• Establish processing budgets and select implementation approaches based on performance and FPGA resources.
• Develop reference models to study radar behavior and guide hardware design decisions.
• Build RTL functions for waveform generation and receive processing in FMCW and pulsed radar.
• Implement processing stages to extract targets from radar returns and apply CFAR.
• Integrate ADC/DAC interfaces and synchronize with the radar front end.
• Verify designs against reference models through testbenches and HDL simulations.
• Investigate performance gaps using lab measurements and field results.

Connaissances

Radar processing

RTL verification

DSP fundamentals

Range-Doppler estimation

CFAR techniques

Matched filtering

Radar system knowledge

HIL testing

Signal processing to RTL

System integration

Formation

Master’s degree in EE / Signal Processing / Applied Physics

Outils

VHDL

Verilog/SystemVerilog

Description du poste

Alta Ares seeks an experienced FPGA engineer to translate radar sensing requirements into RTL in VHDL/Verilog, enabling reliable drone detection for FMCW and pulsed radar systems.

You will collaborate across RF, electronics, and software teams, defining data flow, processing budgets, and implementation approaches while validating designs with testbenches and hardware-in-the-loop testing.