FPGA Engineer: RF DSP & Hardware Optimization

Alta Ares; Paris; Hybride; EUR 65 000 - 90 000; Plein temps

Résumé du poste

Alta Ares is seeking an experienced FPGA engineer to own the development of RTL-based functions for electronic warfare and signals intelligence. You will work with systems and algorithms teams to define processing requirements and validate implementations on operational hardware.

Responsibilities include building RTL modules in VHDL/SystemVerilog for RF signal processing, adapting DSP algorithms for FPGA, and establishing verification methods.

Qualifications

• MSc or higher in Electrical/Electronics Engineering or related field.
• Strong RTL experience with VHDL and SystemVerilog.
• Experience with SoC FPGAs, synthesis, timing analysis and hardware debugging.

Responsabilités

• Own the development of FPGA functions from architecture to validation on hardware.
• Define processing requirements with systems and algorithm engineers.
• Build RTL modules in VHDL or SystemVerilog for RF signal processing.
• Adapt DSP algorithms for FPGA implementation balancing accuracy and resources.
• Integrate acquisition and processing chains and perform tests.
• Establish verification methods and testbenches for functional checks.
• Bring up FPGA designs on target boards and resolve integration issues.
• Maintain design records, interface specs, and validation evidence.

Connaissances

RTL design

VHDL

SystemVerilog

DSP

FPGA validation

Synthesis

Formation

MSc in Electrical Engineering

MSc in Electronics Engineering

Signal Processing

Outils

MATLAB

Simulink

Python

HLS

Description du poste

Alta Ares is seeking an experienced FPGA engineer to own the development of RTL-based functions for electronic warfare and signals intelligence. You will work with systems and algorithms teams to define processing requirements and validate implementations on operational hardware.

Responsibilities include building RTL modules in VHDL/SystemVerilog for RF signal processing, adapting DSP algorithms for FPGA, and establishing verification methods.