Senior Analog Design Engineer – High-Speed SerDes for AI

Kandou Ai; Saint-Sulpice; Presencial; EUR 70.000 - 110.000; Jornada completa

Descripción de la vacante

Kandou is redefining AI hardware with a MIMO-over-copper memory fabric, delivering high-performance, scalable AI systems. We pioneer analog design for Serdes and advanced transceivers, combining deep expertise with a collaborative, design-driven culture.

As an Analog Design Engineer, you will contribute to design, modeling and verification of high-speed analog blocks, coordinate with cross-functional teams and support silicon validation.

Formación

• Master's or PhD in Electronics or related field.
• 5+ years in analog design and layout of high-speed transceivers and RF/multi-tone circuits.
• Expertise in oscillators, PLLs, DLLs and biasing blocks for high-speed analog circuits.
• Experience with modern semiconductor processes, FinFET nodes.
• Experience using Ocean/MDL or similar for automating analog verification.

Responsabilidades

• Position in design, modeling and verification of analog designs for high-speed Serdes in advanced technology nodes.
• Design and verification of analog circuits meeting architecture specs.
• Support and interact with customers on requirements, performance results and delivery.
• Support analog IP and chip-level integration.
• Collaborate with architects, leads, layout, verification and silicon teams.

Conocimientos

Serdes design

Analog circuits

Cadence Virtuoso

EDA tools

Team collaboration

Schedule management

Educación

Master's or PhD in Electronics

Herramientas

Ocean

MDL

Descripción del empleo

Kandou is redefining AI hardware with a MIMO-over-copper memory fabric, delivering high-performance, scalable AI systems. We pioneer analog design for Serdes and advanced transceivers, combining deep expertise with a collaborative, design-driven culture.

As an Analog Design Engineer, you will contribute to design, modeling and verification of high-speed analog blocks, coordinate with cross-functional teams and support silicon validation.