Advanced R&D - Analog Design Engineer

Kandou Ai; Saint-Sulpice; Presencial; EUR 129.000 - 194.000; Jornada completa

Descripción de la vacante

Kandou is redefining AI infrastructure with its MIMO-over-copper technology and energy-efficient, chiplet-based AI memory fabric. The Analog Design Engineer will join the Advanced Research and Development Department in Switzerland to push high-speed analog designs and layout excellence for next-generation AI hardware.

The role covers specification, modeling, verification, layout, post-layout support, and close collaboration with the design team to deliver robust silicon products.

Formación

• Deep understanding of design and layout techniques for high-speed, high-precision circuits.
• Experience in testbenches and simulation setups to analyze performance.
• Expertise in layout matching, parasitic estimation, and submicron challenges.
• Strong knowledge of modern semiconductor processes (CMOS 28nm, FinFET 16/14nm, 7nm).
• Solid background in Signal Processing and Communications.

Responsabilidades

• Develop block level specifications and models for target designs.
• Design, model, verify performance of analog circuits in advanced nodes.
• Layout design and floor-planning with post-layout verification.
• Design verification at pre- and post-layout, including variation-aware checks.
• Collaborate with design/ layout teams and silicon integration engineers.
• Support post-silicon lab bring-up, debugging, characterization, and productization.
• Produce progress and analysis reports; contribute to architecture studies.

Conocimientos

High-speed analog design

Layout techniques

Testbenches & simulations

Cadence Virtuoso

Signal integrity modelling

Communication & reporting

Educación

MSc or PhD in electronics/electrical engineering

Herramientas

Cadence Virtuoso

Spectre/HSpice

Calibre/PVS DRC/LVS

Parasitic extraction & modelling

EM/IR drop tools

ESD analysis

Descripción del empleo

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

Job Title: Analog Design Engineer (Advanced Research and Development Department)

Job Location: Switzerland

Key responsibilities

• Develop block level specifications and models for target designs
• Develop, model, design, and verify performance of custom analog circuits in advanced technology nodes
• Layout design and development, including floor-planning, guiding layout engineers, and post-layout verification
• Design verification at different levels (pre- and post-layout, variation-aware)
• Support and collaborate with the design team, including other design and layout engineers, architects and chip level integration engineers, modeling and system level designers.
• Support for post-silicon lab bring-up, debug, characterization and productization.
• Produce reports (progress report, analysis, design, modeling, and verification reports)
• Participate in developing concept level architectures and circuits

Skills

• Deep understanding on design and layout techniques for high-speed and high-precision circuits, problem solver, and excellent analytical skills.
• Experience in developing testbenches and simulation setups to analyze performance of target circuits and systems.
• Skillful in layout techniques, such as matching, parasitic estimation and reduction, and deep-submicron related issues.
• Advanced user of EDA tool for design and verification, preferably Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitic extraction and modelling, EM and IR drop tools, and ESD analysis, among others.
• Self-motivated, with strong sense of ownership and responsibility.
• Manage workload, schedules and report to internal management and technical teams.
• Excellent communication and reporting skills.

Experience

• 5+ years of experience in design and layout of analog and mixed-signal circuits, especially high-speed and high-precision circuits. Examples are: multi-gigabit serial data-link transceivers, RF circuits, equalizers, clock generators, PLLs, clock and data recovery circuits, data converters (ADC or DAC), biasing and bandgap circuits.
• MSc or PhD in electronics/electrical engineering (equivalent or higher).
• Experienced with modern semiconductor process technologies, such as CMOS 28nm, and FinFET 16/14nm, 7nm.
• Experienced in high-level modelling, top-level simulations, and signal integrity.
• Solid background on Signal Processing and Communications

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