Scale-Up Layout Engineer for Quantum Chips

Alice & Bob; Paris; Hybrid; EUR 70,000 - 110,000; Full time

Job summary

Alice & Bob is building the first universal, fault-tolerant quantum computer. This role focuses on the layout infrastructure—PDK, layout compilers, parasitic extraction, hierarchical verification, and mask generation—to scale chip complexity while keeping design cycles flat.

You will design tile-based methods, write layout generators, and own the end-to-end mask data preparation, with a path toward >1,000 qubit scales and tight integration with the EDA toolchain and EM handoff.

Qualifications

• 5+ years in physical design or mask data prep in a semiconductor context.
• Experience replacing hand-drawn layouts with generators and hierarchical flows.
• Hands-on parasitic extraction and signoff in a fabrication context.

Responsibilities

• Build and own the PDK, layer stack, technology file, parametric cells, and their DRC/LVS decks.
• Design a tile-based, hierarchical layout methodology for wafer-scale and multi-chip designs.
• Write and maintain layout generators that turn architecture spec into DRC-clean GDSII/OASIS.
• Own mask generation end-to-end: floorplan → hierarchical layout → DRC/LVS/PEX signoff → wafer map.
• Drive automation targets toward higher percentages of automated layout across large qubit counts.

Skills

Physical design

Layout automation

Parasitic extraction

Python scripting

GDSII/OASIS

Tools

Calibre xRC/xACT

StarRC

gdstk

gdsfactory

KLayout API

Job description

Alice & Bob is building the first universal, fault-tolerant quantum computer. This role focuses on the layout infrastructure—PDK, layout compilers, parasitic extraction, hierarchical verification, and mask generation—to scale chip complexity while keeping design cycles flat.

You will design tile-based methods, write layout generators, and own the end-to-end mask data preparation, with a path toward >1,000 qubit scales and tight integration with the EDA toolchain and EM handoff.