Quantum Layout Scale-Up Engineer

Alice & Bob; Paris; Remote; EUR 90,000 - 140,000; Full time

Job summary

Alice & Bob in Paris is seeking a senior physical design engineer to build the layout infrastructure for scaling quantum hardware. You will own PDK development, layout compilers, parasitic extraction, and mask generation, enabling multi-chip designs with hierarchical methods.

Role focuses on semiconductor physical design for superconducting hardware, not quantum physics, with a strong emphasis on automation, GDSII/OASIS workflows, and end-to-end tape-out readiness.

Qualifications

• 5+ years in physical design or layout with end-to-end tape-out experience.
• Experience scaling a layout methodology using generators, PCells or hierarchical flows.
• Hands-on parasitic extraction with Calibre, Quantus, StarRC or similar tools.
• Strong scripting: Python (gdstk/gdsfactory) and/or SKILL/Tcl.
• Fluent in DRC/LVS, GDSII/OASIS, reticle constraints and tape-out prep.
• Nice to have superconducting or cryogenic device layout experience.

Responsibilities

• Build the layout infrastructure — PDK, layout compilers, parasitic extraction, hierarchical verification, and mask generation.
• Design a tile-based, hierarchical layout methodology with tiles, instantiation and stitching.
• Write and maintain layout generators turning architecture specs into DRC-clean GDSII/OASIS.
• Own mask generation end-to-end: floorplan to mask data prep and tape-out package.
• Drive automation targets: >50% automated layout at 400 qubits, >80% at 1,000, >90% at 10,000+.
• Keep runtime and file size manageable via hierarchical, cell-level verification.
• Evaluate and deploy EDA toolchain integration with EM-simulation handoff.
• Serve as physical-implementation signoff at design-review gates.

Skills

Layout automation

Parasitic extraction

Deck authoring

Python scripting

GDSII/OASIS handling

Frequency plan to geometry

Tools

Calibre xRC/xACT

Quantus

StarRC

FastCap/FastHenry

BEM/FEM solvers

gdstk

gdsfactory

KLayout API

Job description

Alice & Bob in Paris is seeking a senior physical design engineer to build the layout infrastructure for scaling quantum hardware. You will own PDK development, layout compilers, parasitic extraction, and mask generation, enabling multi-chip designs with hierarchical methods.

Role focuses on semiconductor physical design for superconducting hardware, not quantum physics, with a strong emphasis on automation, GDSII/OASIS workflows, and end-to-end tape-out readiness.