Remote Signal & Power Integrity Engineer for AI Hardware

Spd-Technology; France; Remote; EUR 90,000 - 125,000; Full time

Job summary

SPD Technology is seeking a Signal Integrity/Power Integrity Engineer to join our team, shaping the future of AI/ML hardware acceleration and leading chip and package design from concept to production.

You will drive SI/PI analysis for HPC, collaborate across cross-functional teams, and leverage 2.5D/3D packaging tech to optimize PDN, IPs, and co-design.

Remote-friendly, flexible model, with focus on performance and long-term partnerships.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 8 years of experience in SI/PI design for chip, package, or system PCB.
• Experience with SIPI modeling tool chains (HFSS, ADS, Sigrity, Siwave, etc).
• Experience with lab bring-up, test environments, and characterization for high-speed memory and SerDes.
• Experience with partnering across chip architecture, physical design, static timing analysis (STA), package, and validation teams.
• Experience in Python, MATLAB, or C++ to establish automated flows and data processing tools.

Responsibilities

• Lead SI/PI analysis and optimization for HPC using advanced 2.5D/3D packaging.
• Influence chip floorplanning, PDN, netlists, and routability early in product definition.
• Evaluate high-speed interface IPs and develop memory interfaces across IO PHY, SI/PI, and physical design boundaries.
• Drive post-silicon validation and qualification for NPI, balancing SI/PI performance and DFM constraints to achieve final package design closure.
• Collaborate with silicon, system, and external vendor teams while developing simulation methodologies to boost modeling accuracy and efficiency.

Skills

Python

MATLAB

C++

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

HFSS

ADS

Sigrity

Siwave

Job description

SPD Technology is seeking a Signal Integrity/Power Integrity Engineer to join our team, shaping the future of AI/ML hardware acceleration and leading chip and package design from concept to production.

You will drive SI/PI analysis for HPC, collaborate across cross-functional teams, and leverage 2.5D/3D packaging tech to optimize PDN, IPs, and co-design.

Remote-friendly, flexible model, with focus on performance and long-term partnerships.