Scale-Up Layout Engineer for Quantum Chips

Limelight Health; Paris (TX); On-site; USD 150,000 - 210,000; Full time

Job summary

Alice & Bob is building the first universal, fault-tolerant quantum computer based on Schrödinger cat qubits, targeting scalable chip layouts for thousands of qubits.

This role focuses on physical-design infrastructure, PDK development, and automated flow creation for superconducting hardware. You will implement tile-based layouts, generators, and mask data prep to enable large-scale fabrication.

Qualifications

• 5+ years in physical design, custom/analog layout, PDK development, or mask data prep in a semiconductor context (CMOS backend, RF/analog, MEMS, or photonics).
• Track record scaling a layout methodology—replacing hand-drawn layout with generators, PCells, or hierarchical flows.
• Hands-on parasitic extraction experience—commercial or field-solver-based—and deck/rule-file development.

Responsibilities

• Build and own the PDK — layer stack, technology file, cells, and their DRC/LVS decks.
• Design a tile-based, hierarchical layout methodology with reticle-compatible tiles.
• Write and maintain layout generators turning architecture spec + frequency plan into DRC-clean GDSII/OASIS.
• Own mask generation end-to-end from floorplan to tape-out.
• Drive automation targets: >50% automated layout at 400 qubits, >80% at 1,000, >90% at 10,000+.
• Keep DRC/LVS/PEX runtime and file size tractable at 10^6–10^8 elements.
• Evaluate and deploy the EDA toolchain (Cadence/Siemens/Synopsys) and integrate with EM-simulation.
• Serve as physical-implementation signoff at design review gates ahead of mask release.

Skills

PDK development

Layout automation

Python scripting

GDSII/OASIS

DRC/LVS

Parasitic extraction

Mask data prep

EDA toolchains

Hierarchical layout

Tape-out ownership

Tools

Calibre xRC/xACT

Quantus

StarRC

gdstk

gdsfactory

KLayout API

Cadence

Siemens

Synopsys

Job description

Alice & Bob is building the first universal, fault-tolerant quantum computer based on Schrödinger cat qubits, targeting scalable chip layouts for thousands of qubits.

This role focuses on physical-design infrastructure, PDK development, and automated flow creation for superconducting hardware. You will implement tile-based layouts, generators, and mask data prep to enable large-scale fabrication.