Digital Design Engineer - Sr Staff

TDK InvenSense; Grenoble; On-site; EUR 110,000 - 160,000; Full time

Job summary

TDK InvenSense seeks a Senior Staff Digital Design & Architecture Engineer to lead the definition and implementation of complex digital designs for our MEMS sensor platforms. You will bridge system requirements and silicon, bringing deep expertise in digital architecture, RTL design, and technical leadership.

You will partner with the Digital Design Manager to guide the digital portion of major projects from concept to silicon, mentor junior engineers, and drive design reviews, low-power

Qualifications

• 10+ years of hands-on ASIC/FPGA digital design experience.
• Experience leading complex digital projects from specification to production.
• Strong experience in Mixed-Signal IC environments.

Responsibilities

• Lead digital architecture definition of complex IP blocks for MEMS sensors.
• Perform feasibility studies, power/area estimations, and hardware/software partitioning.
• Drive technical decision-making and ensure alignment with system requirements.
• Define and implement design specifications and documentation.
• Execute RTL design for RTL/IP blocks (Verilog/VHDL).
• Oversee synthesis, STA-Signoff, and CDC checks.
• Collaborate with Analog teams for mixed-signal interfaces.
• Mentor junior/mid-level design engineers; drive flow improvements.
• Present design status and trade-offs to management.

Skills

Digital design leadership

Verilog/VHDL

RTL design

Architecture & system partitioning

Scripting (Python/TCL)

English communication

Mentorship

Cross-functional collaboration

Design reviews

Education

BS in Electrical Engineering or Computer Science

MS or PhD preferred

Tools

Cadence/Synopsys front-end suites (Xcelium, VCS)

Job description

We are looking for a highly experienced Senior Staff Digital Design & Architecture Engineer to lead the definition and implementation of complex digital designs for our next-generation MEMS sensor platforms. The ideal candidate will bridge the gap between system requirements and silicon implementation, possessing deep expertise in digital architecture, RTL design, and technical leadership. You will act as a key technical partner for the Digital Design Manager, helping to lead the digital part of major projects from concept to silicon.

Job Description :

Technical Leadership & Architecture

• Lead the digital architecture definition of complex IP blocks and subsystems for MEMS sensors.
• Perform feasibility studies, power/area estimations, and define hardware/software partitioning.
• Drive technical decision-making and ensure alignment with system-level requirements.
• Define and implement comprehensive design specifications and documentation.

Design & Implementation

• Execute high-quality RTL design (Verilog/VHDL) for critical IPs (e.g., Power Sequencers, Digital Controllers, FSMs).
• Oversee digital front-end activities, including synthesis, STA-Signoff, and CDC checks.
• Collaborate closely with Analog teams to specify and implement complex mixed-signal interfaces.
• Implement low-power design techniques and manage power-up/down sequences for analog components.
• Work closely with Architecture, Analog, Digital Back-End, and Firmware teams to ensure seamless integration.
• Provide technical mentorship to junior and mid-level design engineers, promoting best practices.
• Conduct design reviews and drive continuous improvement of the digital design flow.
• Identify technical risks and develop proactive mitigation strategies.
• Present design status and technical trade-offs to management and stakeholders.
• Participate in post-silicon validation and debug efforts.

Experience & Qualifications :

• 10+ years of hands-on ASIC/FPGA digital design experience.
• Experience in leading complex digital projects from specification to production.
• Strong experience in Mixed-Signal IC environments.

Technical Skills

• Design Languages: Expert-level proficiency in Verilog and/or VHDL.
• ASIC Flow: Deep knowledge of Synthesis (Design Compiler), STA (PrimeTime), and Formal Verification (Formality).
• Protocols: Extensive experience with industry-standard protocols (AMBA AHB/APB/AXI, I2C, I3C, SPI).
• Low Power: Strong knowledge of low-power design and verification techniques (UPF/CPF).
• Tools: Familiarity with Cadence/Synopsys front-end suites (Xcelium, VCS).
• Scripting: Proficiency in Python, TCL, or Shell scripting for flow automation.

Education

• BS in Electrical Engineering or Computer Science required.
• MS or PhD preferred.

Ways to stand out from the crowd:

• Experience with RISC-V, or other processor architectures
• Post-silicon validation and bring-up experience
• Experience with MEMS sensor interfaces

Technical Excellence

• Deep analytical and problem-solving skills for complex architectural challenges.
• Ability to debug complex, multi-million gate designs and mixed-signal loops.
• Strong focus on design quality, documentation, and maintainability.

Leadership & Communication

• Excellent written and verbal communication skills (English is a must).
• Ability to mentor, influence, and lead technical teams without direct hierarchical authority.
• Strong cross-functional collaboration skills to bridge technical silos.

Personal Attributes:

• Self-motivated with strong ownership mentality
• Detail-oriented with quality focus
• Adaptable to changing priorities
• Passion for innovation and continuous learning

InvenSense, a TDK group company, is a world-leading provider of MEMS and magnetic sensor solutions found in mobile, wearable, smart home, AR/VR, and other consumer and IoT applications. We are innovators with a 20+ year history of patented sensor technologies. As experts in our field, we lead industry breakthroughs in consumer, industrial and automotive technology and reliably deliver high-quality solutions to our partners across global markets.

Learn more about us at invensense.tdk.com