Hybrid FPGA Prototyping Engineer: RTL/HDL & Complex Platforms

SiPearl; Grenoble; Hybrid; EUR 65,000 - 90,000; Full time

Benefits offered by this job

Annual bonus

Meal vouchers 60% covered by SiPearl

Health insurance 70% covered by SiPear

Moka.care mental health access

Technical, linguistic and personal dev

BSPCE

Job summary

SiPearl is building an FPGA prototyping platform to validate pre-silicon hardware and firmware. We seek an experienced engineer to design, implement and optimize the FPGA prototyping workflow across HW/SW flows.

You will work on RTL-to-prototype flows, HDL languages, and collaboration with EDA/IP partners, with a strong emphasis on performance, reliability and developer productivity in a fast-growing European team.

Qualifications

• Strong expertise in FPGA development and prototyping on complex platforms.
• Solid knowledge of HDL languages (SystemVerilog, VHDL) and timing constraints (SDC).
• Ability to architect robust solutions and drive continuous improvements.
• Professional proficiency in English in an international environment.
• Strong communication, teamwork and autonomy.
• Scientific rigor, curiosity and problem-solving mindset.

Responsibilities

• Design, develop and continuously improve the FPGA prototyping workflow, integrating it into HW/SW flows.
• Generate, test and debug complex FPGA platforms from RTL, ensuring performance and robustness.
• Develop and integrate hardware and software blocks, plus automation tools and scripts to improve productivity.
• Provide expert-level technical support to internal users and propose scalable solutions.
• Interface with EDA tool vendors and IP providers, driving discussions and tracking resolutions.
• Contribute to technology watch and share best practices across teams.

Skills

FPGA development

HDL languages

SystemVerilog

VHDL

English proficiency

Autonomy

Problem-solving mindset

Job description

SiPearl is building an FPGA prototyping platform to validate pre-silicon hardware and firmware. We seek an experienced engineer to design, implement and optimize the FPGA prototyping workflow across HW/SW flows.

You will work on RTL-to-prototype flows, HDL languages, and collaboration with EDA/IP partners, with a strong emphasis on performance, reliability and developer productivity in a fast-growing European team.