Head - SoC Physical Design Manager

NXP Semiconductors; Valbonne; Presencial; EUR 150.000 - 210.000; Jornada completa

Descripción de la vacante

NXP Semiconductors NV in Valbonne, France, seeks a Head of Physical Design to lead a high‑caliber team responsible for implementation and signoff of advanced ICs and mixed‑signal SoCs. You will shape the strategy and drive performance, power, and area targets across multiple projects.

This role blends deep technical leadership with people development, mentoring engineers, defining methodologies, and ensuring robust verification, P&R, STA, and tape‑out readiness while collaborating with

Formación

• Significant experience in advanced IC/SoC Physical Design, supported by multiple successful tape-outs and ramp of high volume products.
• Deep technical knowledge of the domain ( Place & Route, STA, timing closure, packaging, physical signoff, IR-drop, EM, signal integrity, power integrity and reliability) for low power designs with complex power management
• Deep technical knowledge of the interaction between architecture, RTL, synthesis, DFT, Physical Des

Responsabilidades

• Lead, develop and grow a team of Physical Design, STA and signoff engineers.
• Establish clear technical direction, priorities and accountability across the team.
• Build a strong engineering culture based on technical excellence, collaboration, ownership and continuous improvement.
• Coach and mentor engineers and technical leaders, developing both technical depth and future leadership capability.
• Own the Physical Design strategy and execution for complex IC and mixed-signal SoC developments.
• Lead floorplanning, partitioning, power planning, placement, clock-tree implementation, routing and physical optimization.
• Drive Static Timing Analysis and timing closure, including multi-mode, multi-corner environments.
• Lead implementation and verification of power-management architectures, including multiple voltage domains, power gating, level shifting, isolation and always-on domains.
• Drive power integrity and reliability activities, including IR-drop, electromigration and related physical effects.
• Provide technical leadership for mixed-signal physical integration, particularly at analog/digital interfaces and for noise-sensitive circuitry.
• Ensure robust physical verification and signoff, including DRC, LVS and tape-out readiness.
• Lead technical reviews and provide direction on difficult timing, congestion, power, signal-integrity, reliability and physical-verification challenges.

Conocimientos

Physical Design leadership

Place & Route

STA

Timing closure

Power integrity

IR-drop

Signal integrity

Reliability

Tape-outs

Descripción del empleo

AT STI we develop products that enable trusted physical AI. We are seeking an accomplished Head of Physical Design to lead a highly skilled Physical Design organization responsible for the implementation and signoff of advanced integrated circuits, including complex mixed-signal SoCs.

This is both a technical and people leadership role. You will combine deep expertise in Physical Design with the ability to build, develop and inspire a strong engineering team. You will also collaborate with Physical Design and implementation organizations across NXP, helping to establish and drive common methodologies, best practices, engineering standards and continuous improvement across the company.

You will provide leadership from early physical architecture and floorplanning through Place & Route (P&R), Static Timing Analysis (STA), power and timing closure, physical verification and tape-out, ensuring products achieve their performance, power, area, reliability, quality and schedule objectives.

Lead the Physical Design organization

• Lead, develop and grow a team of highly skilled Physical Design, STA and signoff engineers.
• Establish clear technical direction, priorities and accountability across the team.
• Build a strong engineering culture based on technical excellence, collaboration, ownership and continuous improvement.
• Coach and mentor engineers and technical leaders, developing both technical depth and future leadership capability.
• Identify competency and capability needs and develop the organization to address future technology and product challenges.
• Support resource and capability planning across multiple development programs.
• Create an environment in which engineers can effectively challenge assumptions, identify risks early and drive problems through to resolution.
• Attract and retain strong engineering talent and build an organization capable of delivering increasingly complex designs.

Drive Physical Design and signoff

• Own the Physical Design strategy and execution for complex IC and mixed-signal SoC developments.
• Lead floorplanning, partitioning, power planning, placement, clock-tree implementation, routing and physical optimization.
• Drive Static Timing Analysis and timing closure, including complex multi-mode, multi-corner environments.
• Lead implementation and verification of power-management architectures, including multiple voltage domains, power gating, level shifting, isolation and always-on domains.
• Drive power integrity and reliability activities, including IR-drop, electromigration and related physical effects.
• Provide technical leadership for mixed-signal physical integration, particularly at analog/digital interfaces and for noise-sensitive circuitry.
• Ensure robust physical verification and signoff, including DRC, LVS and tape-out readiness.
• Lead technical reviews and provide direction on difficult timing, congestion, power, signal-integrity, reliability and physical-verification challenges.
• Work closely with architecture and front-end teams to ensure designs are physically achievable and optimized for performance, power and area. A key part of the role is ensuring that physical implementation considerations influence architectural and design decisions early, rather than becoming problems to be resolved late in the development cycle.

Drive best practices across NXP

• Work closely with peer Physical Design teams across NXP to share knowledge, align approaches and develop company-wide best practices.
• Actively contribute to cross-organizational Physical Design and signoff communities, ensuring that lessons learned and successful methodologies are shared beyond individual projects or business groups.
• Identify opportunities to standardize and improve P&R, STA, power, physical-verification and signoff flows across teams.
• Promote reuse of methodologies, automation, scripts, flows and engineering solutions rather than solving similar problems independently in different organizations.
• Benchmark methodologies and results across development teams to identify opportunities for improvement.
• Partner with EDA, methodology, technology, library and IP teams to influence the evolution of the broader IC implementation environment.
• Drive adoption of new methodologies and technologies where they provide measurable improvements in quality, productivity, predictability or PPA.
• Represent the organization in cross-NXP technical discussions and help shape the longer‑term Physical Design strategy and roadmap.

What you bring

• Significant experience in advanced IC/SoC Physical Design, supported by multiple successful tape‑outs and ramp of high volume products.
• Deep technical knowledge of the domain ( Place & Route, STA, timing closure, packaging, physical signoff, IR-drop, EM, signal integrity, power integrity and reliability) for low power designs with complex power management
• Deep technical knowledge of the interaction between architecture, RTL, synthesis, DFT, Physical Des