Chief SoC Physical Design & Signoff Leader

NXP Semiconductors NV; Valbonne; Presencial; EUR 150.000 - 210.000; Jornada completa

Descripción de la vacante

NXP Semiconductors NV in Valbonne, France, seeks a Head of Physical Design to lead a high‑caliber team responsible for implementation and signoff of advanced ICs and mixed‑signal SoCs. You will shape the strategy and drive performance, power, and area targets across multiple projects.

This role blends deep technical leadership with people development, mentoring engineers, defining methodologies, and ensuring robust verification, P&R, STA, and tape‑out readiness while collaborating with

Formación

• Significant experience in advanced IC/SoC Physical Design, supported by multiple successful tape-outs and ramp of high volume products.
• Deep technical knowledge of the domain ( Place & Route, STA, timing closure, packaging, physical signoff, IR-drop, EM, signal integrity, power integrity and reliability) for low power designs with complex power management
• Deep technical knowledge of the interaction between architecture, RTL, synthesis, DFT, Physical Des

Responsabilidades

• Lead, develop and grow a team of Physical Design, STA and signoff engineers.
• Establish clear technical direction, priorities and accountability across the team.
• Build a strong engineering culture based on technical excellence, collaboration, ownership and continuous improvement.
• Coach and mentor engineers and technical leaders, developing both technical depth and future leadership capability.
• Own the Physical Design strategy and execution for complex IC and mixed-signal SoC developments.
• Lead floorplanning, partitioning, power planning, placement, clock-tree implementation, routing and physical optimization.
• Drive Static Timing Analysis and timing closure, including multi-mode, multi-corner environments.
• Lead implementation and verification of power-management architectures, including multiple voltage domains, power gating, level shifting, isolation and always-on domains.
• Drive power integrity and reliability activities, including IR-drop, electromigration and related physical effects.
• Provide technical leadership for mixed-signal physical integration, particularly at analog/digital interfaces and for noise-sensitive circuitry.
• Ensure robust physical verification and signoff, including DRC, LVS and tape-out readiness.
• Lead technical reviews and provide direction on difficult timing, congestion, power, signal-integrity, reliability and physical-verification challenges.

Conocimientos

Physical Design leadership

Place & Route

STA

Timing closure

Power integrity

IR-drop

Signal integrity

Reliability

Tape-outs

Descripción del empleo

NXP Semiconductors NV in Valbonne, France, seeks a Head of Physical Design to lead a high‑caliber team responsible for implementation and signoff of advanced ICs and mixed‑signal SoCs. You will shape the strategy and drive performance, power, and area targets across multiple projects.

This role blends deep technical leadership with people development, mentoring engineers, defining methodologies, and ensuring robust verification, P&R, STA, and tape‑out readiness while collaborating with