Digital Physical Design Engineer

Skills Alliance; France; On-site; EUR 60,000 - 90,000; Full time

Job summary

Skills Alliance seeks a Digital Physical Design Engineer to join our ASIC design team, responsible for physical implementation from RTL handoff to tape-out in France. You will work closely with Front-End Design, DFT, and wider engineering teams to deliver complex ASIC projects from specification through silicon.

The role emphasizes floorplanning, placement and routing, timing closure, and seamless collaboration across design streams to ensure successful tape-out and product delivery.

Qualifications

• Experience in Digital Physical Design or Backend ASIC Design.
• Understanding of the ASIC development lifecycle from specification to tape-out.
• Experience with physical implementation, placement and routing, and timing closure.

Responsibilities

• Implement designs from RTL handoff through to mask generation and tape-out.
• Carry out floorplanning, placement, and routing activities.
• Support timing closure and physical implementation tasks.
• Collaborate with Front-End Design and DFT engineers.
• Contribute to the ASIC design flow from specification to silicon.

Skills

Digital Physical Design

Backend ASIC Design

Timing closure

Placement and routing

Floorplanning

RTL handoff

ASIC development lifecycle

Team collaboration

Tools

Physical design tools

Timing analysis tools

Job description

We are seeking a Digital Physical Design Engineer to join a growing ASIC design team developing advanced semiconductor products. You will be responsible for the physical implementation of digital ASICs, working across the backend design flow from RTL handoff through to tape-out.

Working closely with Front-End Design, DFT, and wider engineering teams, you will contribute to the successful delivery of complex ASIC projects from specification through to silicon.

Key Responsibilities:

• Implement designs from RTL handoff through to mask generation and tape-out.
• Carry out floorplanning, placement, and routing activities.
• Support timing closure and physical implementation tasks.
• Collaborate closely with Front-End Design and DFT engineers.
• Contribute to the overall ASIC design flow from specification to silicon.

Candidate Profile:

• Experience in Digital Physical Design or Backend ASIC Design.
• Strong understanding of the ASIC development lifecycle from specification to tape-out.
• Experience with physical implementation, placement and routing, and timing closure.
• Experience working with Front-End Design and DFT teams.
• Knowledge of ASIC and semiconductor design processes.
• Strong technical troubleshooting and problem-solving skills.