Senior Staff Engineer ASIC Deployment Architect - SoC / ASIC / Interconnect / NoC

European Tech Recruit; Paris; Sur place; EUR 90 000 - 130 000; Plein temps

Résumé du poste

European Tech Recruit is seeking a Senior Staff Engineer specialized in NoC deployment and SoC interconnect architecture. You will lead cross-disciplinary teams across design, verification, emulation, and post-silicon activities to ensure robust NoC integration in complex SoCs.

You will analyze micro-architecture, optimize performance, and resolve silicon bring-up challenges while shaping future interconnect solutions. This role requires senior technical leadership and global collaboration.

Qualifications

• Bachelor's/Master's level in a relevant engineering field.
• Strong knowledge of NoC interconnect technology and IP integration.
• Experience across SoC lifecycle: architecture, RTL, verification, silicon bring-up.

Responsabilités

• Collaborate with SoC Architecture, Hardware Design, Software, Verification, Emulation, Debug, and Post-Silicon teams to ensure efficient deployment and use of NoC technology
• Contribute to the definition of interconnect requirements, architecture, configuration, and implementation across multiple SoC programmes
• Act as a senior technical point of contact for NoC deployment and integration activities
• Provide technical support for new NoC solutions and help engineering teams resolve complex integration challenges
• Analyse and resolve NoC micro-architecture, configuration, performance, and integration issues
• Debug complex SoC issues across simulation, emulation, and silicon bring-up environments
• Participate in defining new NoC solutions, capabilities, methodologies, and technology improvements
• Work closely with architecture and design teams to understand system-level requirements and translate them into effective interconnect configurations

Connaissances

NoC deployment & integration

SoC architecture

AXI/CHI/NoC protocols

RTL design & verification

Debugging across sim/emul/silicon

Formation

Master's in Electrical/Computer Engineering

Outils

Verilog/VHDL

Simulation tools

Emulation platforms

Description du poste

We are currently partnered with a global semiconductor technology company developing advanced interconnect hardware IP, software tools, and SoC integration methodologies designed to help engineering teams build high-performance systems with optimised Power, Performance and Area (PPA).

This is a highly technical, senior-level individual contributor role working at the intersection of SoC architecture, interconnect technology, hardware design, verification, performance optimisation, and silicon deployment. You will collaborate with engineering teams and technical experts globally to ensure NoC technology is effectively integrated and deployed across complex SoC programmes.

Key responsibilities

• Collaborate with SoC Architecture, Hardware Design, Software, Verification, Emulation, Debug, and Post-Silicon teams to ensure efficient deployment and use of NoC technology
• Contribute to the definition of interconnect requirements, architecture, configuration, and implementation across multiple SoC programmes
• Act as a senior technical point of contact for NoC deployment and integration activities
• Provide technical support for new NoC solutions and help engineering teams resolve complex integration challenges
• Analyse and resolve NoC micro-architecture, configuration, performance, and integration issues
• Debug complex SoC issues across simulation, emulation, and silicon bring-up environments
• Participate in defining new NoC solutions, capabilities, methodologies, and technology improvements
• Work closely with architecture and design teams to understand system-level requirements and translate them into effective interconnect configurations

Key requirements

• Strong understanding of the overall SoC development lifecycle, including SoC architecture, RTL design, verification, emulation, physical implementation, silicon bring-up, and debug
• Solid understanding of SoC performance considerations, including DDR memory channels, memory hierarchy, bandwidth, latency, and system-level bottlenecks
• Strong knowledge of system-level concepts including memory mapping, MMUs, Quality of Service (QoS), cache infrastructure, coherency, and security architectures
• Strong analytical and debugging skills across simulation, emulation, and silicon environments
• Good understanding of interconnect technologies and protocols such as AHB, AXI, ACE, ACE-Lite, CHI, and NoC architectures

Keywords

Staff Engineer / Senior Staff Engineer / SoC Architect / ASIC Architect / Solutions Architect / Deployment Architect / SoC Deployment / ASIC / SoC / NoC / Network-on-Chip / Interconnect / Interconnect Architecture / Hardware IP / RTL / SoC Integration / CPU / GPU / Cache / Memory Controller / DDR / Coherency / CHI / ACE / ACE-Lite / AXI / AHB / MMU / QoS / Security / Chiplets / High-Speed Protocols / Verification / Emulation / Silicon Debug / Post-Silicon / PPA / Performance Optimisation / Python / Perl / Semiconductor / Microelectronics / Hardware Architecture / Application Engineering / Technical Support / Debug / Global Engineering / Advanced SoC

By applying to this role, you understand that we may collect your personal data and process it in line with our privacy policy.

https://eu-recruit.com/wp-content/uploads/2025/01/European-Tech-Recruit-Privacy-Notice-2025.pdf