Cutting-Edge Cache Coherence Architect for SoC/NoC

Arteris; Biot; Sur place; EUR 80 000 - 110 000; Plein temps

Résumé du poste

Arteris is seeking a Cache Coherency Architect to define and optimize cache coherency solutions within our NoC IP portfolio. You will develop cutting-edge cache coherent interconnect IP for seamless integration with other NoC IP and system IP, enabling efficient communication across multiple cores and functional units.

You will collaborate with hardware designers, verification engineers, software developers, and stakeholders to deliver high-performance, power-efficient IP.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Proven experience as a Cache Coherency Architect, Design Engineer, or similar role with a focus on NoC IP development.
• In-depth knowledge of SoC and NoC architecture, cache coherency protocols, and memory hierarchy.
• Strong understanding of cache hierarchies and their interaction with NoC interconnects.
• Experience in cache coherency verification and validation techniques.
• Familiarity with hardware description languages (HDLs) and SoC design tools.
• Strong analytical and problem-solving skills with a strategic mindset.
• Excellent communication and collaboration abilities to work effectively with diverse teams and stakeholders.
• Familiarity with HDLs and design tools used in NoC IP development or prior experience in designing coherent systems is highly advantageous.

Responsabilités

• Cache Coherency Architecture: Evaluate existing and industry standard cache coherency protocols, maintain and improve proprietary coherency protocol.
• Develop scalable cache coherency architectures aligned with SoC design.
• Analyze customer requirements for cache coherent system architectures including die-to-die and chip-to-chip designs using CXL, UCIe and PCIe.
• Set performance goals (PPA) for configurable IP.
• NoC Integration: Collaborate with SoC design teams for seamless integration of cache coherency into the SoC architecture.
• Optimize Cache Coherency Architecture and uArchitecture within the NoC to minimize latency and improve BW.
• Performance and Power Optimization: Analyze bottlenecks and propose innovative efficiency solutions.
• Collaborate with hardware and software teams to verify and optimize cache coherency mechanisms.
• Protocol Verification: Support verification team to develop verification strategies for correctness and robustness.
• Assist emulation teams in testing and debugging to validate cache coherency under various scenarios.
• Cross-Functional Collaboration: Interact with marketing and sales to collect customer input and understand market needs.
• Collaborate with hardware design, software development, and system architecture teams.
• Provide technical expertise to assist in product integration.
• Industry Research and Innovation: Stay up-to-date with advancements in cache coherency and NoC technologies.
• Evaluate emerging standards and trends and propose integration.
• Documentation and Communication: Prepare architecture specifications and design guidelines/white papers.

Connaissances

Cache Coherence

NoC Architecture

HDLs & EDA tools

Verifications & testing

Cross-functional collaboration

Documentation

Formation

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

Outils

HDLs

SoC design tools

Description du poste

Arteris is seeking a Cache Coherency Architect to define and optimize cache coherency solutions within our NoC IP portfolio. You will develop cutting-edge cache coherent interconnect IP for seamless integration with other NoC IP and system IP, enabling efficient communication across multiple cores and functional units.

You will collaborate with hardware designers, verification engineers, software developers, and stakeholders to deliver high-performance, power-efficient IP.