SoC Interconnect Technology Team Lead

Arm; Valbonne; On-site; EUR 178,200 - 241,100; Full time

Job summary

Arm is seeking an experienced SoC Interconnect Technology Team Lead to drive architecture, design, and execution of next‑generation interconnect solutions for advanced SoCs. You will lead a high‑performing team focusing on performance, power efficiency, and system‑level optimization across coherent and non‑coherent fabrics.

Requirements include 15+ years in SoC architecture/design with deep interconnect expertise and a track record delivering large‑scale mobile, battery‑powered, or HPC

Qualifications

• 15+ years of experience in SoC architecture/design with a focus on interconnects.
• Proven track record delivering large‑scale SoCs for mobile, battery‑powered or HPC.
• Deep knowledge of coherent interconnect protocols (AMBA ACE/CHI/CHI).
• Strong experience with non‑coherent interconnects (AXI, NoC).
• Expertise in performance analysis, modeling and system trade‑offs.
• Solid memory hierarchy and cache coherency understanding.
• Experience leading cross‑functional teams to tape‑out.

Responsibilities

• Lead architecture and development of coherent and non‑coherent interconnect fabrics.
• Define system‑level interconnect strategies: topology, QoS, latency, bandwidth, power.
• Collaborate with CPU/GPU/NPU/memory and system teams for integration and scaling.
• Drive adoption of industry standards (AMBA AXI/ACE/CHI or equivalent).
• Own performance modeling, analysis, and bottleneck identification.
• Guide microarchitecture, RTL design, and verification for interconnect IP.
• Lead debug and root‑cause analysis of complex system issues.
• Mentor and grow a team of architects and engineers.
• Contribute to roadmap planning for next‑gen interconnect tech.

Skills

SoC architecture

Interconnect fabrics

AMBA ACE/CHI

Coherent/non-coherent interconnects

Performance modeling

Leadership

System-level optimization

Tape-out experience

Job description

We are seeking an experienced SoC Interconnect Technology Team Lead to drive the architecture, design, and execution of next‑generation coherent and non‑coherent interconnect solutions for advanced SoCs. This role requires deep expertise in scalable interconnect fabrics across mobile, battery‑operated, and large‑scale compute systems, with a strong focus on performance, power efficiency, and system‑level optimization. You will lead a high‑performing team responsible for delivering robust interconnect IP and shaping future SoC architectures.

Key Responsibilities

• Lead the architecture and development of coherent and non‑coherent interconnect fabrics for complex SoCs.
• Define and drive system‑level interconnect strategies, including topology, Quality of Service (QoS), latency, bandwidth, and power optimization.
• Collaborate with CPU, GPU, NPU, memory, and system teams to ensure seamless integration and performance scaling.
• Drive adoption and implementation of industry standards (e.g., AMBA AXI/ACE/CHI or equivalent).
• Own performance modeling, analysis, and bottleneck identification across use cases.
• Guide microarchitecture, RTL design, and verification strategy for interconnect IP.
• Lead debug and root‑cause analysis of complex system‑level issues.
• Mentor and grow a team of architects and engineers.
• Contribute to roadmap planning for next‑generation SoC interconnect technologies.

Required Qualifications

• 15+ years of experience in SoC architecture/design, with a focus on interconnects or system fabrics.
• Proven track record of delivering large‑scale SoCs (mobile, battery‑powered, or high‑performance compute platforms).
• Deep understanding of coherent interconnect protocols (e.g., AMBA ACE, CHI, CCIX, CXL, or similar).
• Strong experience with non‑coherent interconnects (AXI, NoC‑based fabrics, etc.).
• Expertise in performance analysis, modeling, and system trade‑offs (latency, bandwidth, power).
• Solid knowledge of cache coherency, memory hierarchy, and system architecture.
• Experience leading cross‑functional teams and driving complex projects to tape‑out.

Preferred Qualifications

• Experience with battery‑optimized SoC design (low power, DVFS, power domains).
• Familiarity with AI/ML accelerators, GPUs, or heterogeneous compute systems.
• Exposure to network‑on‑chip (NoC) design methodologies and tools.
• Experience with silicon bring‑up and post‑silicon validation.
• Strong leadership, communication, and stakeholder management skills.

What You’ll Bring

• Strategic thinking with strong execution capability.
• Ability to influence architecture across multiple subsystems.
• Passion for building scalable, high‑performance, and power‑efficient systems.
• A track record of mentoring and building high‑impact teams.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Salary Range: €178,200 - €241,100 per year