SoC Physical Design Engineer — Tape-Out & Power

Sine-Engineering; Tampere; On-site; EUR 60,000 - 90,000; Full time

Benefits offered by this job

Lunch Benefit

Wellbeing Allowance

Extended Healthcare

Accident Insurance

Job summary

Sine Engineering in Tampere, Finland seeks a Physical Design Engineer to help build next‑generation SoCs from ground up. You’ll drive the RTL‑to‑GDSII flow, optimize timing, power, and test and contribute to tape-out for scalable multi‑drone autonomy platforms.

From synthesis to sign-off, you’ll work with senior engineers using industry‑standard tools, strong debugging, and a proactive, ownership‑driven mindset. This is a hands‑on role offering growth and cutting‑edge challenges.

Qualifications

• Background in SoC physical design, from recent graduates to senior engineers.
• Experience with RTL-to-GDSII flow (synthesis, P&R, STA, physical verification).
• Familiarity with industry-standard EDA tools (Synopsys, Cadence, Siemens).
• Solid understanding of timing analysis, CDC, and low-power design methodologies.
• Proficiency in Tcl, Python, or Perl for flow automation and analysis.
• Strong debugging skills and a proactive ownership mindset.

Responsibilities

• Drive the physical implementation flow from synthesis through place-and-route and GDSII sign-off.
• Contribute to floorplanning, power planning, timing closure, and sign-off.
• Perform DRC/LVS/antenna checks and electromigration/IR-drop analysis.
• Manage DFT integration including scan insertion and test pattern generation flows.
• Support UPF/CPF power-aware design, power domain planning, and retention strategies.
• Coordinate with package/board teams for tape-out and co-design.

Skills

SoC design

RTL-to-GDSII flow

Timing analysis

Low-power design

DFT concepts

Scripting: Tcl/Python/Perl

Tools

Synopsys Design Compiler

Fusion Compiler

IC Compiler

Cadence Genus

Innovus

Calibre (Siemens)

Job description

Sine Engineering in Tampere, Finland seeks a Physical Design Engineer to help build next‑generation SoCs from ground up. You’ll drive the RTL‑to‑GDSII flow, optimize timing, power, and test and contribute to tape-out for scalable multi‑drone autonomy platforms.

From synthesis to sign-off, you’ll work with senior engineers using industry‑standard tools, strong debugging, and a proactive, ownership‑driven mindset. This is a hands‑on role offering growth and cutting‑edge challenges.