SoC Physical Design Engineer — Drive Tapeouts & Timing

Sine Eng; Tampere; On-site; EUR 70,000 - 110,000; Full time

Benefits offered by this job

Lunch Benefit

Sport & Culture Benefit

Wellbeing Allowance

Extended Occupational Healthcare

24/7 Accident Insurance

Business Travel Insurance

Company Phone & Subscription

Office Perks

Job summary

Sine Engineering seeks a Physical Design Engineer (all levels) to join our team in Tampere. You will drive the physical implementation of next-generation SoCs, from synthesis to GDSII sign-off, and collaborate across front-end, back-end, and package teams.

Responsibilities include floorplanning, timing closure, physical verification, DFT integration, low-power flows, and tape-out preparation. Strong candidates have project experience and a proactive ownership mindset.

Qualifications

• Background in SoC physical design with project experience or senior level experience.
• Experience with the RTL-to-GDSII flow and timing closure.
• Familiarity with industry-standard EDA tools (Synopsys, Cadence, Siemens or equivalent).
• Solid understanding of timing analysis, CDC, low-power design methodologies, and DFT concepts.
• Scripting proficiency in Tcl, Python, or Perl for flows and analysis.
• Strong debugging skills and a proactive ownership mindset.

Responsibilities

• Drive the physical implementation flow from synthesis through place-and-route, timing closure, and GDSII sign-off.
• Contribute to floorplanning, power planning, placement, clock tree synthesis, and routing for SoC blocks and full-chip integration.
• Perform timing closure across PVT corners and operating modes including STA and ECO planning.
• Conduct physical verification (DRC/LVS/ERC), antenna checks, and electromigration/IR-drop analysis.
• Lead DFT integration including scan insertion, compression, MBIST, boundary scan, and test pattern generation flows.
• Support low-power implementation with UPF/CPF co-design, power domains, level shifters, isolation, and retention strategies.
• Coordinate package definition and co-design, including pinout planning and package-aware PI.
• Prepare tape-out and sign-off with GDSII generation and foundry deliverables.

Skills

SoC Design

RTL-to-GDSII

Timing analysis

Tcl/Python/Perl

Debugging

Ownership mindset

Scripting automation

Tools

Synopsys Design Compiler

Fusion Compiler

IC Compiler

Cadence Genus

Innovus

Calibre

Job description

Sine Engineering seeks a Physical Design Engineer (all levels) to join our team in Tampere. You will drive the physical implementation of next-generation SoCs, from synthesis to GDSII sign-off, and collaborate across front-end, back-end, and package teams.

Responsibilities include floorplanning, timing closure, physical verification, DFT integration, low-power flows, and tape-out preparation. Strong candidates have project experience and a proactive ownership mindset.