Physical Design Engineer

Sine Eng; Tampere; On-site; EUR 70,000 - 110,000; Full time

Benefits offered by this job

Lunch Benefit

Sport & Culture Benefit

Wellbeing Allowance

Extended Occupational Healthcare

24/7 Accident Insurance

Business Travel Insurance

Company Phone & Subscription

Office Perks

Job summary

Sine Engineering seeks a Physical Design Engineer (all levels) to join our team in Tampere. You will drive the physical implementation of next-generation SoCs, from synthesis to GDSII sign-off, and collaborate across front-end, back-end, and package teams.

Responsibilities include floorplanning, timing closure, physical verification, DFT integration, low-power flows, and tape-out preparation. Strong candidates have project experience and a proactive ownership mindset.

Qualifications

• Background in SoC physical design with project experience or senior level experience.
• Experience with the RTL-to-GDSII flow and timing closure.
• Familiarity with industry-standard EDA tools (Synopsys, Cadence, Siemens or equivalent).
• Solid understanding of timing analysis, CDC, low-power design methodologies, and DFT concepts.
• Scripting proficiency in Tcl, Python, or Perl for flows and analysis.
• Strong debugging skills and a proactive ownership mindset.

Responsibilities

• Drive the physical implementation flow from synthesis through place-and-route, timing closure, and GDSII sign-off.
• Contribute to floorplanning, power planning, placement, clock tree synthesis, and routing for SoC blocks and full-chip integration.
• Perform timing closure across PVT corners and operating modes including STA and ECO planning.
• Conduct physical verification (DRC/LVS/ERC), antenna checks, and electromigration/IR-drop analysis.
• Lead DFT integration including scan insertion, compression, MBIST, boundary scan, and test pattern generation flows.
• Support low-power implementation with UPF/CPF co-design, power domains, level shifters, isolation, and retention strategies.
• Coordinate package definition and co-design, including pinout planning and package-aware PI.
• Prepare tape-out and sign-off with GDSII generation and foundry deliverables.

Skills

SoC Design

RTL-to-GDSII

Timing analysis

Tcl/Python/Perl

Debugging

Ownership mindset

Scripting automation

Tools

Synopsys Design Compiler

Fusion Compiler

IC Compiler

Cadence Genus

Innovus

Calibre

Job description

About Sine Engineering

Sine Engineering builds the technology behind reliable drone autonomy, including communications, navigation, and control systems that enable coordinated multi-drone operations at scale. More than 200 UAV manufacturers rely on our technology, and our solutions power many of today's active interceptor operations.

Through our dual-use platform, we support civilian innovation while helping democratic nations strengthen their technological advantage.

Any drone. Any scale. Anywhere.

We build resilient communication, navigation, and coordination systems for the age of autonomy.

We are looking for Physical Design Engineer (all levels) to join our team in building next-generation System-on-Chips (SoCs) from the ground up.

Responsibilities

Drive the physical implementation flow, from synthesis through place-and-route, timing closure, and GDSII sign-off.

Contribute to one or more of the following areas:

• Synthesis and constraint development (SDC), including handoff between front-end and back-end teams.

• Floorplanning, power planning, placement, clock tree synthesis, and routing for SoC blocks and full-chip integration.

• Timing closure across PVT corners and operating modes, including STA, ECO planning, and sign-off.

• Physical verification, including DRC, LVS, ERC, antenna checks, and electromigration/IR-drop analysis.

• DFT integration and implementation, including scan insertion, compression, MBIST, boundary scan, and ownership of test pattern generation flows.

• Low-power implementation, including UPF/CPF co-design flows, power domains, level shifters, isolation, and retention strategies.

• Package definition and co-design, including pinout planning, bump/ball assignment, package-aware signal and power integrity, and collaboration with package and board teams.

• Tape-out preparation and sign-off, including GDSII generation, foundry deliverables, and DRC/LVS-clean handoff.

Skills and Requirements

• Background in SoC physical design, ranging from recent graduates with strong fundamentals and relevant project experience to senior engineers with multiple successful tape-outs.

• Working knowledge of the complete RTL-to-GDSII flow (appropriate to experience level), including synthesis, place-and-route, STA, and physical verification.

• Familiarity with industry-standard EDA tools such as Synopsys Design Compiler, Fusion Compiler, IC Compiler, Cadence Genus, Innovus, Siemens Calibre, or equivalent solutions.

• Solid understanding of timing analysis, CDC, low-power design methodologies, and design-for-test concepts.

• Scripting proficiency in Tcl, Python, or Perl for flow automation and analysis.

• Strong debugging skills and a structured approach to resolving complex implementation challenges.

• A proactive attitude, strong ownership mindset, and eagerness to learn and grow with the team.

Nice to Have

• Experience with package definition, pinout optimization, and package/PCB co-design.

• Experience with mixed-signal or RF SoC implementation and analog-to-digital integration.

• Knowledge of signal integrity, power integrity, and electromigration analysis.

• Experience with hierarchical implementation methodologies and large-block partitioning.

What We Offer

Time Off

• Paid time off in accordance with Finnish labor legislation.

Health & Wellness Benefits

• Lunch Benefit: Daily lunch allowance up to the tax-free limit.

• Sport & Culture Benefit: Annual budget for gym memberships, sports activities, cultural events, and hobbies.

• Wellbeing Allowance: Additional support for massages, mental health services, and other wellness-related activities.

• Extended Occupational Healthcare: Enhanced coverage including GP visits, specialist care, mental health support, and partial dental coverage.

• 24/7 Accident Insurance: Coverage during both work and personal time.

• Business Travel Insurance: Comprehensive coverage for work-related travel.

• Company Phone & Subscription: Provided as an employee benefit.

• Office Perks: Complimentary coffee, snacks, fruit, and other office amenities.

Work Environment

• No-Crunch Culture: No systematic overtime. Any overtime is compensated in accordance with company policy.

• Meeting-Light Culture: Protected focus time with minimal unnecessary meetings.

• Low-Hierarchy Environment: High autonomy, strong ownership, and zero micromanagement.

Growth & Innovation

• High-End Equipment: Premium laptop, monitor, and peripherals.

• Lab & Gadget Budget: Annual budget for hardware, tools, books, and learning materials.

• Hackathons & Offsites: Regular events focused on innovation, experimentation, and technology.

Travel & Mobility

• Full reimbursement of business travel expenses, including transportation and accommodation.

• Daily per diem allowances based on the maximum tax-free rates published by the Finnish Tax Administration (Vero).

Privacy Notice

By applying for this position, you consent to the processing of your personal data for recruitment purposes.

Your personal data will be processed in accordance with the EU General Data Protection Regulation (GDPR) and the Finnish Act on the Protection of Privacy in Working Life.

Application data will be retained for a maximum of six months unless you explicitly consent to a longer retention period.

You may request access to, correction of, or deletion of your personal data at any time by contacting:

[e-mail]