SoC Physical Design Engineer – Timing & Tape-Out

Sine Engineering; Tampere; On-site; EUR 65,000 - 95,000; Full time

Benefits offered by this job

Lunch Benefit

Sport & Culture Benefit

Wellbeing Allowance

Extended Occupational Healthcare

24/7 Accident Insurance

Business Travel Insurance

Company Phone & Subscription

Office Perks

Job summary

Sine Engineering is seeking a Physical Design Engineer (all levels) to join our team in Tampere to drive the RTL-to-GDSII flow for complex SoCs. You will own synthesis, place-and-route, timing closure, and sign-off across multiple projects with high autonomy.

The role involves collaboration with back-end teams, DFT integration, low-power flows, and tape-out preparation. We value proactive learners who can tackle challenging implementation issues and contribute to a no-crunch culture.

Qualifications

• Background in SoC physical design with project experience.
• Proficiency in RTL-to-GDSII flow including synthesis, place-and-route, STA and physical verification.
• Familiarity with industry-standard EDA tools (Synopsys, Cadence, Siemens).
• Strong timing analysis, CDC, low-power design methods, and design-for-test concepts.
• Scripting proficiency in Tcl, Python, or Perl for flow automation and analysis.

Responsibilities

• Drive the physical implementation flow from synthesis through place-and-route and GDSII sign-off.
• Contribute to floorplanning, power planning, placement, clock tree synthesis and routing.
• Ensure timing closure across PVT corners and operating modes; plan ECOs.
• Handle physical verification (DRC/LVS/ERC/antenna checks) and DFT integration.
• Support low-power implementation, UPF/CPF flows, and power-domain planning.
• Coordinate with package, board, and back-end teams for tape-out prep.

Skills

SoC physical design

RTL-to-GDSII flow

Scripting (Tcl/Python/Perl)

Debugging

Ownership & initiative

Tools

Synopsys Design Compiler

Fusion Compiler

IC Compiler

Cadence Genus

Innovus

Calibre

Job description

Sine Engineering is seeking a Physical Design Engineer (all levels) to join our team in Tampere to drive the RTL-to-GDSII flow for complex SoCs. You will own synthesis, place-and-route, timing closure, and sign-off across multiple projects with high autonomy.

The role involves collaboration with back-end teams, DFT integration, low-power flows, and tape-out preparation. We value proactive learners who can tackle challenging implementation issues and contribute to a no-crunch culture.