ASIC Digital Synthesis Engineer

Swedium Global Services AB; Oulu; Hybrid; EUR 70,000 - 110,000; Full time

Job summary

Swedium Global Services AB in Finland is seeking an ASIC Digital Synthesis Engineer to drive timing closure, RTL-to-gate synthesis, STA, and power-aware design. You will optimize performance, power, and area while meeting project requirements and collaborate with DFT and digital design teams.

The role requires several years of chip implementation experience, proficiency with Synopsys and Cadence tools, scripting in TCL/Python, and strong English communication.

Qualifications

• BSc/MSc in Electronics Engineering or equivalent.
• Several years of chip implementation experience.
• Experience with Synopsys/Cadence IC implementation and verification tools.
• Scripting languages knowledge (TCL, Perl, Python).
• Excellent written and verbal communication in English.

Responsibilities

• Develop, refine, and validate timing constraints to ensure accurate implementation and timing analysis.
• Perform RTL-to-gate logic synthesis, optimizing for performance, power, and area while meeting project requirements.
• Conduct comprehensive Static Timing Analysis (STA) across multiple corners.
• Drive timing closure activities with ECOs to meet performance and schedule targets.
• Perform logic equivalence checking between RTL, synthesized nets, and post-ECO implementations.
• Execute low-power verification and analysis to ensure power intent compliance.
• Collaborate with DFT team to integrate test structures and ensure manufacturable silicon.
• Partner with design teams to translate design intent into implementation and provide guidance.

Skills

Scripting languages (TCL, Perl, Python

English communication

AI knowledge

Chip implementation experience

Flow development

Education

BSc/MSc in Electronics Engineering or similar

Tools

Synopsys IC implementation tools

Cadence IC verification/signoff tools

AI-assisted EDA flows

Job description

Swedium Global Services is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.

Location - Onsite, Finland

Job Title - ASIC Digital Synthesis Engineer

We are hiringexperienced engineers with knowledge of synthesis and static timing analysis (STA). .

Key responsibilities

Develop, refine, and validate timing constraints to ensure accurate implementation and timing analysis

Perform RTL-to-gate logic synthesis, optimizing designs for performance, power, and area while meeting project requirements.

Conduct comprehensive Static Timing Analysis (STA) to identify, analyze, and resolve timing issues across multiple operating conditions and process corners.

Drive timing closure activities by implementing and evaluating ECOs, ensuring designs meet performance and schedule targets.

Perform logic equivalence checking to verify functional consistency between RTL, synthesized netlists, and post-ECO implementations.

Execute low-power verification and analysis to ensure compliance with power intent specifications and support energy-efficient product development.

Collaborate closely with the Design-for-Test (DFT) team to integrate test structures, achieve high test coverage, and ensure manufacturable, testable silicon.

Partner with digital design and architecture teams to translate design intent into implementation, providing feedback and guidance to meet functional, performance, and timing objectives.

Qualification and skills

BSc/MSc in Electronics Engineering or similar

Several years of experience in chip implementation

Experience of relevant Synopsys and Cadence IC implementation and verification / signoff tools

Contribution to flow development and setup

Knowledge of scripting languages like TCL, Perl, Python or similar

Experience using AI-assisted tools to improve design productivity (e.g. AI-driven EDA flows, code/script generation, debug assistance)

Excellent written and verbal communication skills in English

Job Overview

• Vacancy : 1
• Key Skills : Good to have AI knowledge and Synopysis Flow