Senior RTL Verification Engineer

Swediumglobal; Tampere; On-site; EUR 45,000 - 65,000; Full time

Job summary

Swediumglobal in Tampere is seeking a skilled professional for RTL verification of complex SoC and IP designs. The role requires collaboration with design and FPGA teams and developing UVM testbenches.

Ideal candidates have strong experience with SystemVerilog and SoC verification. The position prefers onsite presence, although hybrid models may be considered. Join us in a fast-growing environment that values proactive and independent thinkers.

Qualifications

• Independent and proactive working style.
• Strong debugging and problem-solving skills.
• Comfortable working in a cross‑functional international team.

Responsibilities

• RTL-level verification of complex SoC and IP designs.
• Work closely with design, FPGA, and embedded software teams.
• Develop, extend, and maintain UVM testbench environments.

Skills

Strong hands-on experience in RTL Verification

Excellent knowledge of SystemVerilog

Experience with SoC and/or IP-level verification

Familiarity with regression testing

Ability to analyze failures

Tools

Python

TCL

Bash

Job description

Swedium Global Services is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.

Location - Onsite, Finland

Job Description

The role focuses on RTL-level verification of complex SoC and IP designs, working closely with design, FPGA and embedded software teams in a hardware-centric development environment.

Key Requirements

• Strong hands-on experience in RTL Verification
• Excellent knowledge of SystemVerilog and UVM
• Experience with SoC and/or IP-level verification
• Verification planning, test development, execution, and debugging
• Experience developing, extending, and maintaining UVM testbench environments
• Familiarity with regression testing and coverage-driven verification
• Ability to analyze failures and collaborate with design teams to resolve issues

Preferred Skills

• Experience with ASIC or SoC development programs
• SystemVerilog Assertions (SVA)
• VHDL
• Python, TCL, Bash, or similar scripting languages
• Functional and code coverage analysis
• FPGA prototyping or post-silicon validation experience

Profile

• Independent and proactive working style
• Strong debugging and problem-solving skills
• Comfortable working in a cross‑functional international team

Location

• Tampere, Finland
• Onsite presence preferred (hybrid model may be considered)

Job Overview

• Location : Tampere, Finland
• Vacancy : 1
• Key Skills : ASIC,IP/SOC,UVM,Systemverilog