ASIC Digital Synthesis Engineer — Onsite in Finland

Swedium Global Services AB; Oulu; Hybrid; EUR 70,000 - 110,000; Full time

Job summary

Swedium Global Services AB in Finland is seeking an ASIC Digital Synthesis Engineer to drive timing closure, RTL-to-gate synthesis, STA, and power-aware design. You will optimize performance, power, and area while meeting project requirements and collaborate with DFT and digital design teams.

The role requires several years of chip implementation experience, proficiency with Synopsys and Cadence tools, scripting in TCL/Python, and strong English communication.

Qualifications

• BSc/MSc in Electronics Engineering or equivalent.
• Several years of chip implementation experience.
• Experience with Synopsys/Cadence IC implementation and verification tools.
• Scripting languages knowledge (TCL, Perl, Python).
• Excellent written and verbal communication in English.

Responsibilities

• Develop, refine, and validate timing constraints to ensure accurate implementation and timing analysis.
• Perform RTL-to-gate logic synthesis, optimizing for performance, power, and area while meeting project requirements.
• Conduct comprehensive Static Timing Analysis (STA) across multiple corners.
• Drive timing closure activities with ECOs to meet performance and schedule targets.
• Perform logic equivalence checking between RTL, synthesized nets, and post-ECO implementations.
• Execute low-power verification and analysis to ensure power intent compliance.
• Collaborate with DFT team to integrate test structures and ensure manufacturable silicon.
• Partner with design teams to translate design intent into implementation and provide guidance.

Skills

Scripting languages (TCL, Perl, Python

English communication

AI knowledge

Chip implementation experience

Flow development

Education

BSc/MSc in Electronics Engineering or similar

Tools

Synopsys IC implementation tools

Cadence IC verification/signoff tools

AI-assisted EDA flows

Job description

Swedium Global Services AB in Finland is seeking an ASIC Digital Synthesis Engineer to drive timing closure, RTL-to-gate synthesis, STA, and power-aware design. You will optimize performance, power, and area while meeting project requirements and collaborate with DFT and digital design teams.

The role requires several years of chip implementation experience, proficiency with Synopsys and Cadence tools, scripting in TCL/Python, and strong English communication.