SoC Verification Engineer — SystemVerilog & UVM Expert

TechTeamz; Valencia; Presencial; EUR 45.000 - 65.000; Jornada completa

Descripción de la vacante

TechTeamz in Valencia, Spain, seeks a Digital Design Verification Engineer to verify complex mixed-signal ICs and advanced SoCs, collaborating with multidisciplinary teams from concept to tape-out.

You'll apply SystemVerilog and UVM testbenches, develop verification plans, achieve coverage goals, and run constrained-random verification using Python/Perl/TCL with standard EDA tools, while communicating in English.

Formación

• Hands-on experience in ASIC/FPGA digital design verification for mixed-signal or SoCs.
• Expertise in SystemVerilog and UVM-based testbench architectures.
• Experience with verification plans, coverage closure, and constrained-random verification.
• Proficiency in Python, Perl, or TCL and standard EDA simulation tools.
• Strong problem-solving, teamwork, and English communication skills.

Conocimientos

SystemVerilog

UVM-based testbench

Verification planning

Code/functional coverage

Constrained-random verification

Python scripting

Perl scripting

TCL scripting

Teamwork & communication

English proficiency

Educación

Bachelor's degree in Electrical Engineering or related field

Herramientas

EDA simulators

Python

Perl

TCL

Descripción del empleo

TechTeamz in Valencia, Spain, seeks a Digital Design Verification Engineer to verify complex mixed-signal ICs and advanced SoCs, collaborating with multidisciplinary teams from concept to tape-out.

You'll apply SystemVerilog and UVM testbenches, develop verification plans, achieve coverage goals, and run constrained-random verification using Python/Perl/TCL with standard EDA tools, while communicating in English.